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9952f6918d
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
126 lines
3.1 KiB
ArmAsm
126 lines
3.1 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2014-2015 Altera Corporation. All rights reserved.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#define MAX_LOOP_COUNT 1000
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/* Register offset */
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#define SDR_CTRLGRP_LOWPWREQ_ADDR 0x54
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#define SDR_CTRLGRP_LOWPWRACK_ADDR 0x58
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/* Bitfield positions */
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#define SELFRSHREQ_POS 3
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#define SELFRSHREQ_MASK 0x8
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#define SELFRFSHACK_POS 1
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#define SELFRFSHACK_MASK 0x2
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/*
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* This code assumes that when the bootloader configured
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* the sdram controller for the DDR on the board it
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* configured the following fields depending on the DDR
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* vendor/configuration:
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*
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* sdr.ctrlcfg.lowpwreq.selfrfshmask
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* sdr.ctrlcfg.lowpwrtiming.clkdisablecycles
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* sdr.ctrlcfg.dramtiming4.selfrfshexit
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*/
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.arch armv7-a
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.text
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.align 3
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/*
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* socfpga_sdram_self_refresh
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*
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* r0 : sdr_ctl_base_addr
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* r1 : temp storage of return value
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* r2 : temp storage of register values
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* r3 : loop counter
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*
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* return value: lower 16 bits: loop count going into self refresh
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* upper 16 bits: loop count exiting self refresh
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*/
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ENTRY(socfpga_sdram_self_refresh)
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/* Enable dynamic clock gating in the Power Control Register. */
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mrc p15, 0, r2, c15, c0, 0
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orr r2, r2, #1
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mcr p15, 0, r2, c15, c0, 0
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/* Enable self refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 1 */
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ldr r2, [r0, #SDR_CTRLGRP_LOWPWREQ_ADDR]
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orr r2, r2, #SELFRSHREQ_MASK
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str r2, [r0, #SDR_CTRLGRP_LOWPWREQ_ADDR]
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/* Poll until sdr.ctrlgrp.lowpwrack.selfrfshack == 1 or hit max loops */
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mov r3, #0
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while_ack_0:
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ldr r2, [r0, #SDR_CTRLGRP_LOWPWRACK_ADDR]
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and r2, r2, #SELFRFSHACK_MASK
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cmp r2, #SELFRFSHACK_MASK
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beq ack_1
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add r3, #1
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cmp r3, #MAX_LOOP_COUNT
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bne while_ack_0
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ack_1:
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mov r1, r3
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/*
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* Execute an ISB instruction to ensure that all of the
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* CP15 register changes have been committed.
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*/
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isb
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/*
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* Execute a barrier instruction to ensure that all cache,
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* TLB and branch predictor maintenance operations issued
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* by any CPU in the cluster have completed.
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*/
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dsb
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dmb
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wfi
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/* Disable self-refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 0 */
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ldr r2, [r0, #SDR_CTRLGRP_LOWPWREQ_ADDR]
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bic r2, r2, #SELFRSHREQ_MASK
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str r2, [r0, #SDR_CTRLGRP_LOWPWREQ_ADDR]
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/* Poll until sdr.ctrlgrp.lowpwrack.selfrfshack == 0 or hit max loops */
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mov r3, #0
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while_ack_1:
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ldr r2, [r0, #SDR_CTRLGRP_LOWPWRACK_ADDR]
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and r2, r2, #SELFRFSHACK_MASK
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cmp r2, #SELFRFSHACK_MASK
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bne ack_0
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add r3, #1
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cmp r3, #MAX_LOOP_COUNT
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bne while_ack_1
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ack_0:
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/*
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* Prepare return value:
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* Shift loop count for exiting self refresh into upper 16 bits.
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* Leave loop count for requesting self refresh in lower 16 bits.
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*/
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mov r3, r3, lsl #16
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add r1, r1, r3
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/* Disable dynamic clock gating in the Power Control Register. */
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mrc p15, 0, r2, c15, c0, 0
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bic r2, r2, #1
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mcr p15, 0, r2, c15, c0, 0
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mov r0, r1 @ return value
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bx lr @ return
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ENDPROC(socfpga_sdram_self_refresh)
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ENTRY(socfpga_sdram_self_refresh_sz)
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.word . - socfpga_sdram_self_refresh
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