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https://github.com/brain-hackers/linux-brain.git
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92685e4a28
Add busfreq support for i.MX6SLL. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
461 lines
9.2 KiB
ArmAsm
461 lines
9.2 KiB
ArmAsm
/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/linkage.h>
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#include "hardware.h"
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#define CCM_CBCDR 0x14
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#define CCM_CBCMR 0x18
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#define CCM_CSCMR1 0x1c
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#define CCM_CDHIPR 0x48
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#define L2_CACHE_SYNC 0x730
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#define PL310_AUX_CTRL 0x104
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#define PL310_DCACHE_LOCKDOWN_BASE 0x900
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#define PL310_AUX_16WAY_BIT 0x10000
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#define PL310_LOCKDOWN_NBREGS 8
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#define PL310_LOCKDOWN_SZREG 4
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#define PL310_8WAYS_MASK 0x00FF
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#define PL310_16WAYS_UPPERMASK 0xFF00
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#define MMDC0_MDPDC 0x4
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#define MMDC0_MAPSR 0x404
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#define MMDC0_MADPCR0 0x410
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#define HIGH_BUS_MODE 0x0
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.macro wait_for_ccm_handshake
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1:
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ldr r8, [r2, #CCM_CDHIPR]
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cmp r8, #0
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bne 1b
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.endm
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.macro switch_to_24MHz
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/* periph2_clk2 sel to OSC_CLK */
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ldr r8, [r2, #CCM_CBCMR]
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orr r8, r8, #(1 << 20)
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str r8, [r2, #CCM_CBCMR]
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/* periph2_clk2_podf to 0 */
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ldr r8, [r2, #CCM_CBCDR]
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bic r8, r8, #0x7
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str r8, [r2, #CCM_CBCDR]
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/* periph2_clk sel to periph2_clk2 */
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ldr r8, [r2, #CCM_CBCDR]
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orr r8, r8, #(0x1 << 26)
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str r8, [r2, #CCM_CBCDR]
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wait_for_ccm_handshake
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/* fabric_mmdc_podf to 0 */
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ldr r8, [r2, #CCM_CBCDR]
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bic r8, r8, #(0x7 << 3)
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str r8, [r2, #CCM_CBCDR]
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wait_for_ccm_handshake
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.endm
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.macro switch_to_100MHz
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/* check whether periph2_clk is from top path */
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ldr r8, [r2, #CCM_CBCDR]
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ands r8, #(1 << 26)
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beq skip_periph2_clk2_switch_100m
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/* now switch periph2_clk back. */
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ldr r8, [r2, #CCM_CBCDR]
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bic r8, r8, #(1 << 26)
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str r8, [r2, #CCM_CBCDR]
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wait_for_ccm_handshake
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/*
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* on i.MX6SLL, pre_periph2_clk will be always from
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* pll2_pfd2, so no need to set pre_periph2_clk
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* parent, just set the mmdc divider directly.
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*/
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skip_periph2_clk2_switch_100m:
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/* fabric_mmdc_podf to 3 so that mmdc is 400 / 4 = 100MHz */
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ldr r8, [r2, #CCM_CBCDR]
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bic r8, r8, #(0x7 << 3)
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orr r8, r8, #(0x3 << 3)
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str r8, [r2, #CCM_CBCDR]
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wait_for_ccm_handshake
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.endm
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.macro switch_to_400MHz
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/* check whether periph2_clk is from top path */
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ldr r8, [r2, #CCM_CBCDR]
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ands r8, #(1 << 26)
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beq skip_periph2_clk2_switch_400m
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/* now switch periph2_clk back. */
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ldr r8, [r2, #CCM_CBCDR]
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bic r8, r8, #(1 << 26)
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str r8, [r2, #CCM_CBCDR]
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wait_for_ccm_handshake
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/*
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* on i.MX6SLL, pre_periph2_clk will be always from
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* pll2_pfd2, so no need to set pre_periph2_clk
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* parent, just set the mmdc divider directly.
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*/
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skip_periph2_clk2_switch_400m:
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/* fabric_mmdc_podf to 0 */
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ldr r8, [r2, #CCM_CBCDR]
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bic r8, r8, #(0x7 << 3)
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str r8, [r2, #CCM_CBCDR]
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wait_for_ccm_handshake
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.endm
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.macro mmdc_clk_lower_100MHz
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/* if MMDC is not in 400MHz mode, skip double mu count */
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cmp r1, #HIGH_BUS_MODE
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bne 1f
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/*
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* Prior to reducing the DDR frequency (at 528/400 MHz),
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* read the Measure unit count bits (MU_UNIT_DEL_NUM)
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*/
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ldr r8, =0x8B8
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ldr r6, [r5, r8]
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/* Original MU unit count */
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mov r6, r6, LSR #16
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ldr r4, =0x3FF
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and r6, r6, r4
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/* Original MU unit count * 2 */
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mov r7, r6, LSL #1
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/*
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* Bypass the automatic measure unit when below 100 MHz
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* by setting the Measure unit bypass enable bit (MU_BYP_EN)
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*/
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ldr r6, [r5, r8]
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orr r6, r6, #0x400
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str r6, [r5, r8]
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/*
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* Double the measure count value read in step 1 and program it in the
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* measurement bypass bits (MU_BYP_VAL) of the MMDC PHY Measure Unit
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* Register for the reduced frequency operation below 100 MHz
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*/
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ldr r6, [r5, r8]
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ldr r4, =0x3FF
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bic r6, r6, r4
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orr r6, r6, r7
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str r6, [r5, r8]
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/* For freq lower than 100MHz, need to set RALAT to 2 */
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ldr r6, [r5, #0x18]
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bic r6, r6, #(0x7 << 6)
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orr r6, r6, #(0x2 << 6)
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str r6, [r5, #0x18]
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1:
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.endm
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.macro mmdc_clk_above_100MHz
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/* Make sure that the PHY measurement unit is NOT in bypass mode */
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ldr r8, =0x8B8
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ldr r6, [r5, r8]
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bic r6, r6, #0x400
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str r6, [r5, r8]
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/* Now perform a Force Measurement. */
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ldr r6, [r5, r8]
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orr r6, r6, #0x800
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str r6, [r5, r8]
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/* Wait for FRC_MSR to clear. */
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force_measure1:
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ldr r6, [r5, r8]
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and r6, r6, #0x800
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cmp r6, #0x0
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bne force_measure1
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/* For freq higher than 100MHz, need to set RALAT to 5 */
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ldr r6, [r5, #0x18]
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bic r6, r6, #(0x7 << 6)
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orr r6, r6, #(0x5 << 6)
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str r6, [r5, #0x18]
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.endm
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.align 3
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/*
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* Below code can be used by i.MX6SLL when changing the
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* frequency of MMDC. the MMDC is the same on these two SOCs.
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*/
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ENTRY(imx6sll_lpddr2_freq_change)
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push {r2 - r8}
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/*
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* To ensure no page table walks occur in DDR, we
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* have a another page table stored in IRAM that only
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* contains entries pointing to IRAM, AIPS1 and AIPS2.
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* We need to set the TTBR1 to the new IRAM TLB.
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* Do the following steps:
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* 1. Flush the Branch Target Address Cache (BTAC)
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* 2. Set TTBR1 to point to IRAM page table.
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* 3. Disable page table walks in TTBR0 (PD0 = 1)
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* 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0
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* and 2-4G is translated by TTBR1.
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*/
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ldr r6, =iram_tlb_phys_addr
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ldr r7, [r6]
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/* Flush the Branch Target Address Cache (BTAC) */
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ldr r6, =0x0
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mcr p15, 0, r6, c7, c1, 6
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/* Disable Branch Prediction, Z bit in SCTLR. */
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mrc p15, 0, r6, c1, c0, 0
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bic r6, r6, #0x800
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mcr p15, 0, r6, c1, c0, 0
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dsb
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isb
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/* Store the IRAM table in TTBR1 */
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mcr p15, 0, r7, c2, c0, 1
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/* Read TTBCR and set PD0=1, N = 1 */
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mrc p15, 0, r6, c2, c0, 2
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orr r6, r6, #0x11
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mcr p15, 0, r6, c2, c0, 2
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dsb
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isb
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/* flush the TLB */
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ldr r6, =0x0
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mcr p15, 0, r6, c8, c3, 0
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/* Disable L1 data cache. */
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mrc p15, 0, r6, c1, c0, 0
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bic r6, r6, #0x4
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mcr p15, 0, r6, c1, c0, 0
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dsb
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isb
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#ifdef CONFIG_CACHE_L2X0
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/*
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* Need to make sure the buffers in L2 are drained.
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* Performing a sync operation does this.
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*/
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ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR)
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mov r6, #0x0
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str r6, [r7, #L2_CACHE_SYNC]
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/*
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* The second dsb might be needed to keep cache sync (device write)
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* ordering with the memory accesses before it.
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*/
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dsb
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isb
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ldr r3, [r7, #PL310_AUX_CTRL]
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tst r3, #PL310_AUX_16WAY_BIT
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mov r3, #PL310_8WAYS_MASK
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orrne r3, #PL310_16WAYS_UPPERMASK
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mov r6, #PL310_LOCKDOWN_NBREGS
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add r5, r7, #PL310_DCACHE_LOCKDOWN_BASE
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1: /* lock Dcache and Icache */
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str r3, [r5], #PL310_LOCKDOWN_SZREG
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str r3, [r5], #PL310_LOCKDOWN_SZREG
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subs r6, r6, #1
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bne 1b
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#endif
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ldr r2, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR)
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ldr r3, =IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR)
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ldr r5, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR)
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/* Disable Automatic power savings. */
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ldr r6, [r5, #MMDC0_MAPSR]
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orr r6, r6, #0x1
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str r6, [r5, #MMDC0_MAPSR]
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/* Delay for a while */
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ldr r8, =10
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delay:
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ldr r7, =0
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cont:
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ldr r6, [r5, r7]
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add r7, r7, #4
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cmp r7, #16
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bne cont
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sub r8, r8, #1
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cmp r8, #0
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bgt delay
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/* Make the DDR explicitly enter self-refresh. */
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ldr r6, [r5, #MMDC0_MAPSR]
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orr r6, r6, #0x200000
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str r6, [r5, #MMDC0_MAPSR]
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poll_dvfs_set_1:
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ldr r6, [r5, #MMDC0_MAPSR]
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and r6, r6, #0x2000000
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cmp r6, #0x2000000
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bne poll_dvfs_set_1
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/* set SBS step-by-step mode */
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ldr r6, [r5, #MMDC0_MADPCR0]
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orr r6, r6, #0x100
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str r6, [r5, #MMDC0_MADPCR0]
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ldr r6, =100000000
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cmp r0, r6
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bgt set_ddr_mu_above_100
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mmdc_clk_lower_100MHz
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set_ddr_mu_above_100:
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ldr r6, =24000000
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cmp r0, r6
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beq set_to_24MHz
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ldr r6, =100000000
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cmp r0, r6
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beq set_to_100MHz
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switch_to_400MHz
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mmdc_clk_above_100MHz
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b done
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set_to_24MHz:
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switch_to_24MHz
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b done
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set_to_100MHz:
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switch_to_100MHz
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done:
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/* clear DVFS - exit from self refresh mode */
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ldr r6, [r5, #MMDC0_MAPSR]
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bic r6, r6, #0x200000
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str r6, [r5, #MMDC0_MAPSR]
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poll_dvfs_clear_1:
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ldr r6, [r5, #MMDC0_MAPSR]
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and r6, r6, #0x2000000
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cmp r6, #0x2000000
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beq poll_dvfs_clear_1
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/* Enable Automatic power savings. */
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ldr r6, [r5, #MMDC0_MAPSR]
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bic r6, r6, #0x1
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str r6, [r5, #MMDC0_MAPSR]
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/* clear SBS - unblock DDR accesses */
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ldr r6, [r5, #MMDC0_MADPCR0]
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bic r6, r6, #0x100
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str r6, [r5, #MMDC0_MADPCR0]
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ldr r6, =0xa0000000
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str r6, [r5, #0x83c]
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#ifdef CONFIG_CACHE_L2X0
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ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR)
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ldr r3, [r7, #PL310_AUX_CTRL]
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tst r3, #PL310_AUX_16WAY_BIT
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mov r6, #PL310_LOCKDOWN_NBREGS
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mov r3, #0x00 /* 8 ways mask */
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orrne r3, #0x0000 /* 16 ways mask */
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add r5, r7, #PL310_DCACHE_LOCKDOWN_BASE
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1: /* lock Dcache and Icache */
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str r3, [r5], #PL310_LOCKDOWN_SZREG
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str r3, [r5], #PL310_LOCKDOWN_SZREG
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subs r6, r6, #1
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bne 1b
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#endif
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/* Enable L1 data cache. */
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mrc p15, 0, r6, c1, c0, 0
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orr r6, r6, #0x4
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mcr p15, 0, r6, c1, c0, 0
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/* Restore the TTBCR */
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dsb
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isb
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/* Read TTBCR and set PD0=0, N = 0 */
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mrc p15, 0, r6, c2, c0, 2
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bic r6, r6, #0x11
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mcr p15, 0, r6, c2, c0, 2
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dsb
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isb
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/* flush the TLB */
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ldr r6, =0x0
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mcr p15, 0, r6, c8, c3, 0
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dsb
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isb
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/* Enable Branch Prediction, Z bit in SCTLR. */
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mrc p15, 0, r6, c1, c0, 0
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orr r6, r6, #0x800
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mcr p15, 0, r6, c1, c0, 0
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/* Flush the Branch Target Address Cache (BTAC) */
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ldr r6, =0x0
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mcr p15, 0, r6, c7, c1, 6
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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/* Restore registers */
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pop {r2 - r8}
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mov pc, lr
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