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1f6b6e8a89
This patch adds i.MX6SX bus-freq support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
765 lines
15 KiB
ArmAsm
765 lines
15 KiB
ArmAsm
/*
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* Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/linkage.h>
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#include "hardware.h"
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.globl imx6_up_ddr3_freq_change_start
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.globl imx6_up_ddr3_freq_change_end
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#define MMDC0_MDPDC 0x4
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#define MMDC0_MDCF0 0xc
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#define MMDC0_MDCF1 0x10
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#define MMDC0_MDMISC 0x18
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#define MMDC0_MDSCR 0x1c
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#define MMDC0_MAPSR 0x404
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#define MMDC0_MADPCR0 0x410
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#define MMDC0_MPZQHWCTRL 0x800
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#define MMDC0_MPODTCTRL 0x818
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#define MMDC0_MPDGCTRL0 0x83c
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#define MMDC0_MPMUR0 0x8b8
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#define CCM_CBCDR 0x14
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#define CCM_CBCMR 0x18
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#define CCM_CSCMR1 0x1c
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#define CCM_CDHIPR 0x48
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#define L2_CACHE_SYNC 0x730
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#define PL310_AUX_CTRL 0x104
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#define PL310_DCACHE_LOCKDOWN_BASE 0x900
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#define PL310_AUX_16WAY_BIT 0x10000
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#define PL310_LOCKDOWN_NBREGS 8
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#define PL310_LOCKDOWN_SZREG 4
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#define PL310_8WAYS_MASK 0x00FF
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#define PL310_16WAYS_UPPERMASK 0xFF00
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#define BUSFREQ_INFO_FREQ_OFFSET 0x0
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#define BUSFREQ_INFO_DDR_SETTINGS_OFFSET 0x4
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#define BUSFREQ_INFO_DLL_OFF_OFFSET 0x8
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#define BUSFREQ_INFO_IOMUX_OFFSETS_OFFSET 0xc
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#define BUSFREQ_INFO_MU_DELAY_OFFSET 0x10
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.extern iram_tlb_phys_addr
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.align 3
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/* Check if the cpu is cortex-a7 */
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.macro is_ca7
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/* Read the primary cpu number is MPIDR */
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mrc p15, 0, r7, c0, c0, 0
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ldr r8, =0xfff0
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and r7, r7, r8
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ldr r8, =0xc070
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cmp r7, r8
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.endm
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.macro do_delay
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1:
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ldr r9, =0
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2:
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ldr r10, [r4, r9]
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add r9, r9, #4
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cmp r9, #16
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bne 2b
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sub r8, r8, #1
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cmp r8, #0
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bgt 1b
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.endm
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.macro wait_for_ccm_handshake
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3:
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ldr r8, [r5, #CCM_CDHIPR]
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cmp r8, #0
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bne 3b
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.endm
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.macro switch_to_400MHz
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/* check whether periph2_clk is already from top path */
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ldr r8, [r5, #CCM_CBCDR]
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ands r8, #(1 << 26)
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beq skip_periph2_clk2_switch_400m
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/* now switch periph2_clk back. */
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ldr r8, [r5, #CCM_CBCDR]
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bic r8, r8, #(1 << 26)
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str r8, [r5, #CCM_CBCDR]
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wait_for_ccm_handshake
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/*
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* on i.MX6SX, pre_periph2_clk will be always from
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* pll2_pfd2, so no need to set pre_periph2_clk
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* parent, just set the mmdc divider directly.
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*/
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skip_periph2_clk2_switch_400m:
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/* fabric_mmdc_podf to 0 */
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ldr r8, [r5, #CCM_CBCDR]
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bic r8, r8, #(0x7 << 3)
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str r8, [r5, #CCM_CBCDR]
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wait_for_ccm_handshake
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.endm
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.macro switch_to_50MHz
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/* check whether periph2_clk is already from top path */
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ldr r8, [r5, #CCM_CBCDR]
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ands r8, #(1 << 26)
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beq skip_periph2_clk2_switch_50m
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/* now switch periph2_clk back. */
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ldr r8, [r5, #CCM_CBCDR]
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bic r8, r8, #(1 << 26)
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str r8, [r5, #CCM_CBCDR]
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wait_for_ccm_handshake
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/*
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* on i.MX6SX, pre_periph2_clk will be always from
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* pll2_pfd2, so no need to set pre_periph2_clk
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* parent, just set the mmdc divider directly.
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*/
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skip_periph2_clk2_switch_50m:
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/* fabric_mmdc_podf to 7 so that mmdc is 400 / 8 = 50MHz */
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ldr r8, [r5, #CCM_CBCDR]
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orr r8, r8, #(0x7 << 3)
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str r8, [r5, #CCM_CBCDR]
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wait_for_ccm_handshake
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.endm
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.macro switch_to_24MHz
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/* periph2_clk2 sel to OSC_CLK */
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ldr r8, [r5, #CCM_CBCMR]
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orr r8, r8, #(1 << 20)
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str r8, [r5, #CCM_CBCMR]
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/* periph2_clk2_podf to 0 */
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ldr r8, [r5, #CCM_CBCDR]
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bic r8, r8, #0x7
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str r8, [r5, #CCM_CBCDR]
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/* periph2_clk sel to periph2_clk2 */
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ldr r8, [r5, #CCM_CBCDR]
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orr r8, r8, #(0x1 << 26)
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str r8, [r5, #CCM_CBCDR]
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wait_for_ccm_handshake
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/* fabric_mmdc_podf to 0 */
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ldr r8, [r5, #CCM_CBCDR]
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bic r8, r8, #(0x7 << 3)
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str r8, [r5, #CCM_CBCDR]
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wait_for_ccm_handshake
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.endm
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/*
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* imx6_up_ddr3_freq_change
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* Below code can be used by i.MX6SX and i.MX6UL.
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*
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* idle the processor (eg, wait for interrupt).
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* make sure DDR is in self-refresh.
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* IRQs are already disabled.
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*/
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ENTRY(imx6_up_ddr3_freq_change)
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imx6_up_ddr3_freq_change_start:
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stmfd sp!, {r4 - r11}
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ldr r1, [r0, #BUSFREQ_INFO_DDR_SETTINGS_OFFSET]
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ldr r2, [r0, #BUSFREQ_INFO_DLL_OFF_OFFSET]
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ldr r3, [r0, #BUSFREQ_INFO_IOMUX_OFFSETS_OFFSET]
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/*
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* To ensure no page table walks occur in DDR, we
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* have a another page table stored in IRAM that only
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* contains entries pointing to IRAM, AIPS1 and AIPS2.
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* We need to set the TTBR1 to the new IRAM TLB.
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* Do the following steps:
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* 1. Flush the Branch Target Address Cache (BTAC)
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* 2. Set TTBR1 to point to IRAM page table.
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* 3. Disable page table walks in TTBR0 (PD0 = 1)
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* 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0
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* and 2-4G is translated by TTBR1.
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*/
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ldr r6, =iram_tlb_phys_addr
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ldr r7, [r6]
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/* Disable Branch Prediction, Z bit in SCTLR. */
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mrc p15, 0, r6, c1, c0, 0
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bic r6, r6, #0x800
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mcr p15, 0, r6, c1, c0, 0
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/* Flush the Branch Target Address Cache (BTAC) */
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ldr r6, =0x0
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mcr p15, 0, r6, c7, c1, 6
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dsb
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isb
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/* Store the IRAM table in TTBR1 */
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mcr p15, 0, r7, c2, c0, 1
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/* Read TTBCR and set PD0=1, N = 1 */
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mrc p15, 0, r6, c2, c0, 2
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orr r6, r6, #0x11
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mcr p15, 0, r6, c2, c0, 2
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dsb
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isb
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/* flush the TLB */
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ldr r6, =0x0
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mcr p15, 0, r6, c8, c3, 0
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dsb
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isb
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/* Disable L1 data cache. */
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mrc p15, 0, r6, c1, c0, 0
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bic r6, r6, #0x4
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mcr p15, 0, r6, c1, c0, 0
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ldr r4, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR)
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ldr r5, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR)
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ldr r6, =IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR)
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is_ca7
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beq skip_disable_l2
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#ifdef CONFIG_CACHE_L2X0
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/*
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* make sure the L2 buffers are drained,
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* sync operation on L2 drains the buffers.
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*/
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ldr r8, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR)
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/* Wait for background operations to complete. */
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wait_for_l2_to_idle:
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ldr r7, [r8, #0x730]
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cmp r7, #0x0
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bne wait_for_l2_to_idle
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mov r7, #0x0
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str r7, [r8, #L2_CACHE_SYNC]
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/* Lock L2. */
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ldr r9, [r8, #PL310_AUX_CTRL]
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tst r9, #PL310_AUX_16WAY_BIT
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mov r9, #PL310_8WAYS_MASK
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orrne r9, #PL310_16WAYS_UPPERMASK
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mov r10, #PL310_LOCKDOWN_NBREGS
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add r11, r8, #PL310_DCACHE_LOCKDOWN_BASE
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1: /* lock Dcache and Icache */
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str r9, [r11], #PL310_LOCKDOWN_SZREG
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str r9, [r11], #PL310_LOCKDOWN_SZREG
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subs r10, r10, #1
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bne 1b
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/*
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* The second dsb might be needed to keep cache sync (device write)
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* ordering with the memory accesses before it.
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*/
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dsb
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isb
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#endif
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skip_disable_l2:
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/* disable automatic power saving. */
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ldr r8, [r4, #MMDC0_MAPSR]
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orr r8, r8, #0x1
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str r8, [r4, #MMDC0_MAPSR]
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/* disable MMDC power down timer. */
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ldr r8, [r4, #MMDC0_MDPDC]
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bic r8, r8, #(0xff << 8)
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str r8, [r4, #MMDC0_MDPDC]
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/* delay for a while */
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ldr r8, =4
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do_delay
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/* set CON_REG */
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ldr r8, =0x8000
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str r8, [r4, #MMDC0_MDSCR]
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poll_conreq_set_1:
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ldr r8, [r4, #MMDC0_MDSCR]
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and r8, r8, #(0x4 << 12)
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cmp r8, #(0x4 << 12)
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bne poll_conreq_set_1
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/*
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* if requested frequency is greater than
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* 300MHz go to DLL on mode.
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*/
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ldr r8, [r0, #BUSFREQ_INFO_FREQ_OFFSET]
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ldr r9, =300000000
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cmp r8, r9
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bge dll_on_mode
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dll_off_mode:
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/* if DLL is currently on, turn it off. */
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cmp r2, #1
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beq continue_dll_off_1
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ldr r8, =0x00018031
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str r8, [r4, #MMDC0_MDSCR]
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ldr r8, =0x00018039
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str r8, [r4, #MMDC0_MDSCR]
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ldr r8, =10
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do_delay
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continue_dll_off_1:
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/* set DVFS - enter self refresh mode */
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ldr r8, [r4, #MMDC0_MAPSR]
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orr r8, r8, #(1 << 21)
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str r8, [r4, #MMDC0_MAPSR]
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/* de-assert con_req */
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mov r8, #0x0
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str r8, [r4, #MMDC0_MDSCR]
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poll_dvfs_set_1:
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ldr r8, [r4, #MMDC0_MAPSR]
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and r8, r8, #(1 << 25)
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cmp r8, #(1 << 25)
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bne poll_dvfs_set_1
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ldr r8, [r0, #BUSFREQ_INFO_FREQ_OFFSET]
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ldr r9, =24000000
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cmp r8, r9
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beq switch_freq_24
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switch_to_50MHz
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b continue_dll_off_2
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switch_freq_24:
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switch_to_24MHz
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continue_dll_off_2:
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/* set SBS - block ddr accesses */
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ldr r8, [r4, #MMDC0_MADPCR0]
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orr r8, r8, #(1 << 8)
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str r8, [r4, #MMDC0_MADPCR0]
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/* clear DVFS - exit from self refresh mode */
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ldr r8, [r4, #MMDC0_MAPSR]
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bic r8, r8, #(1 << 21)
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str r8, [r4, #MMDC0_MAPSR]
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poll_dvfs_clear_1:
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ldr r8, [r4, #MMDC0_MAPSR]
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and r8, r8, #(1 << 25)
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cmp r8, #(1 << 25)
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beq poll_dvfs_clear_1
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/* if DLL was previously on, continue DLL off routine. */
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cmp r2, #1
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beq continue_dll_off_3
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ldr r8, =0x00018031
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str r8, [r4, #MMDC0_MDSCR]
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ldr r8, =0x00018039
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str r8, [r4, #MMDC0_MDSCR]
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ldr r8, =0x04208030
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str r8, [r4, #MMDC0_MDSCR]
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ldr r8, =0x04208038
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str r8, [r4, #MMDC0_MDSCR]
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ldr r8, =0x00088032
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str r8, [r4, #MMDC0_MDSCR]
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ldr r8, =0x0008803A
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str r8, [r4, #MMDC0_MDSCR]
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/* delay for a while. */
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ldr r8, =4
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do_delay
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ldr r8, [r4, #MMDC0_MDCF0]
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bic r8, r8, #0xf
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orr r8, r8, #0x3
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str r8, [r4, #MMDC0_MDCF0]
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ldr r8, [r4, #MMDC0_MDCF1]
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bic r8, r8, #0x7
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orr r8, r8, #0x4
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str r8, [r4, #MMDC0_MDCF1]
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ldr r8, [r4, #MMDC0_MDMISC]
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bic r8, r8, #(0x3 << 16) /* walat = 0x1 */
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orr r8, r8, #(0x1 << 16)
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bic r8, r8, #(0x7 << 6) /* ralat = 0x2 */
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orr r8, r8, #(0x2 << 6)
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str r8, [r4, #MMDC0_MDMISC]
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/* enable dqs pull down in the IOMUX. */
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ldr r8, [r3]
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add r3, r3, #8
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ldr r9, =0x3028
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update_iomux:
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ldr r10, [r3]
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ldr r11, [r6, r10]
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bic r11, r11, r9
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orr r11, r11, #(0x3 << 12)
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orr r11, r11, #0x28
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str r11, [r6, r10]
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add r3, r3, #8
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sub r8, r8, #1
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cmp r8, #0
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bgt update_iomux
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/* ODT disabled. */
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ldr r8, =0x0
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str r8, [r4, #MMDC0_MPODTCTRL]
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/* DQS gating disabled. */
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ldr r8, [r4, #MMDC0_MPDGCTRL0]
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orr r8, r8, #(1 << 29)
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str r8, [r4, #MMDC0_MPDGCTRL0]
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/* Add workaround for ERR005778.*/
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/* double the original MU_UNIT_DEL_NUM. */
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ldr r8, [r0, #BUSFREQ_INFO_MU_DELAY_OFFSET]
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lsl r8, r8, #1
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/* Bypass the automatic MU by setting the mu_byp_en */
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ldr r10, [r4, #MMDC0_MPMUR0]
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orr r10, r10, #0x400
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/* Set the MU_BYP_VAL */
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orr r10, r10, r8
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str r10, [r4, #MMDC0_MPMUR0]
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/* Now perform a force measure */
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ldr r8, [r4, #MMDC0_MPMUR0]
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orr r8, r8, #0x800
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str r8, [r4, #MMDC0_MPMUR0]
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/* Wait for FRC_MSR to clear. */
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1:
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ldr r8, [r4, #MMDC0_MPMUR0]
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and r8, r8, #0x800
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cmp r8, #0x0
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bne 1b
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continue_dll_off_3:
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/* clear SBS - unblock accesses to DDR. */
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ldr r8, [r4, #MMDC0_MADPCR0]
|
|
bic r8, r8, #(0x1 << 8)
|
|
str r8, [r4, #MMDC0_MADPCR0]
|
|
|
|
mov r8, #0x0
|
|
str r8, [r4, #MMDC0_MDSCR]
|
|
poll_conreq_clear_1:
|
|
ldr r8, [r4, #MMDC0_MDSCR]
|
|
and r8, r8, #(0x4 << 12)
|
|
cmp r8, #(0x4 << 12)
|
|
beq poll_conreq_clear_1
|
|
|
|
b done
|
|
|
|
dll_on_mode:
|
|
/* assert DVFS - enter self refresh mode. */
|
|
ldr r8, [r4, #MMDC0_MAPSR]
|
|
orr r8, r8, #(1 << 21)
|
|
str r8, [r4, #MMDC0_MAPSR]
|
|
|
|
/* de-assert CON_REQ. */
|
|
mov r8, #0x0
|
|
str r8, [r4, #MMDC0_MDSCR]
|
|
|
|
/* poll DVFS ack. */
|
|
poll_dvfs_set_2:
|
|
ldr r8, [r4, #MMDC0_MAPSR]
|
|
and r8, r8, #(1 << 25)
|
|
cmp r8, #(1 << 25)
|
|
bne poll_dvfs_set_2
|
|
|
|
switch_to_400MHz
|
|
|
|
/* set SBS step-by-step mode. */
|
|
ldr r8, [r4, #MMDC0_MADPCR0]
|
|
orr r8, r8, #(1 << 8)
|
|
str r8, [r4, #MMDC0_MADPCR0]
|
|
|
|
/* clear DVFS - exit self refresh mode. */
|
|
ldr r8, [r4, #MMDC0_MAPSR]
|
|
bic r8, r8, #(1 << 21)
|
|
str r8, [r4, #MMDC0_MAPSR]
|
|
|
|
poll_dvfs_clear_2:
|
|
ldr r8, [r4, #MMDC0_MAPSR]
|
|
ands r8, r8, #(1 << 25)
|
|
bne poll_dvfs_clear_2
|
|
|
|
/* if DLL is currently off, turn it back on. */
|
|
cmp r2, #0
|
|
beq update_calibration_only
|
|
|
|
/* issue zq calibration command */
|
|
ldr r8, [r4, #MMDC0_MPZQHWCTRL]
|
|
orr r8, r8, #0x3
|
|
str r8, [r4, #MMDC0_MPZQHWCTRL]
|
|
|
|
/* enable DQS gating. */
|
|
ldr r10, =MMDC0_MPDGCTRL0
|
|
ldr r8, [r4, r10]
|
|
bic r8, r8, #(1 << 29)
|
|
str r8, [r4, r10]
|
|
|
|
/* Now perform a force measure */
|
|
ldr r8, =0x00000800
|
|
str r8, [r4, #MMDC0_MPMUR0]
|
|
/* Wait for FRC_MSR to clear. */
|
|
1:
|
|
ldr r8, [r4, #MMDC0_MPMUR0]
|
|
and r8, r8, #0x800
|
|
cmp r8, #0x0
|
|
bne 1b
|
|
|
|
/* disable dqs pull down in the IOMUX. */
|
|
ldr r8, [r3]
|
|
add r3, r3, #8
|
|
update_iomux1:
|
|
ldr r10, [r3, #0x0]
|
|
ldr r11, [r3, #0x4]
|
|
str r11, [r6, r10]
|
|
add r3, r3, #8
|
|
sub r8, r8, #1
|
|
cmp r8, #0
|
|
bgt update_iomux1
|
|
|
|
/* config MMDC timings to 400MHz. */
|
|
ldr r1, [r0, #BUSFREQ_INFO_DDR_SETTINGS_OFFSET]
|
|
ldr r7, [r1]
|
|
add r1, r1, #8
|
|
ldr r10, [r1, #0x0]
|
|
ldr r11, [r1, #0x4]
|
|
str r11, [r4, r10]
|
|
add r1, r1, #8
|
|
|
|
ldr r10, [r1, #0x0]
|
|
ldr r11, [r1, #0x4]
|
|
str r11, [r4, r10]
|
|
add r1, r1, #8
|
|
|
|
/* configure ddr devices to dll on, odt. */
|
|
ldr r8, =0x00028031
|
|
str r8, [r4, #MMDC0_MDSCR]
|
|
|
|
ldr r8, =0x00028039
|
|
str r8, [r4, #MMDC0_MDSCR]
|
|
|
|
/* delay for while. */
|
|
ldr r8, =4
|
|
do_delay
|
|
|
|
/* reset dll. */
|
|
ldr r8, =0x09208030
|
|
str r8, [r4, #MMDC0_MDSCR]
|
|
|
|
ldr r8, =0x09208038
|
|
str r8, [r4, #MMDC0_MDSCR]
|
|
|
|
/* delay for while. */
|
|
ldr r8, =100
|
|
do_delay
|
|
|
|
ldr r10, [r1, #0x0]
|
|
ldr r11, [r1, #0x4]
|
|
str r11, [r4, r10]
|
|
add r1, r1, #8
|
|
|
|
ldr r10, [r1, #0x0]
|
|
ldr r11, [r1, #0x4]
|
|
str r11, [r4, r10]
|
|
add r1, r1, #8
|
|
|
|
ldr r8, =0x00428031
|
|
str r8, [r4, #MMDC0_MDSCR]
|
|
|
|
ldr r8, =0x00428039
|
|
str r8, [r4, #MMDC0_MDSCR]
|
|
|
|
ldr r10, [r1, #0x0]
|
|
ldr r11, [r1, #0x4]
|
|
str r11, [r4, r10]
|
|
add r1, r1, #8
|
|
|
|
ldr r10, [r1, #0x0]
|
|
ldr r11, [r1, #0x4]
|
|
str r11, [r4, r10]
|
|
add r1, r1, #8
|
|
|
|
/* issue a zq command. */
|
|
ldr r8, =0x04008040
|
|
str r8, [r4, #MMDC0_MDSCR]
|
|
|
|
ldr r8, =0x04008048
|
|
str r8, [r4, #MMDC0_MDSCR]
|
|
|
|
/* MMDC ODT enable. */
|
|
ldr r10, [r1, #0x0]
|
|
ldr r11, [r1, #0x4]
|
|
str r11, [r4, r10]
|
|
add r1, r1, #8
|
|
|
|
/* delay for while. */
|
|
ldr r8, =40
|
|
do_delay
|
|
|
|
/* enable MMDC power down timer. */
|
|
ldr r8, [r4, #MMDC0_MDPDC]
|
|
orr r8, r8, #(0x55 << 8)
|
|
str r8, [r4, #MMDC0_MDPDC]
|
|
|
|
b update_calibration
|
|
|
|
update_calibration_only:
|
|
ldr r8, [r1]
|
|
sub r8, r8, #7
|
|
add r1, r1, #64
|
|
b update_calib
|
|
|
|
update_calibration:
|
|
/* write the new calibration values. */
|
|
mov r8, r7
|
|
sub r8, r8, #7
|
|
|
|
update_calib:
|
|
ldr r10, [r1, #0x0]
|
|
ldr r11, [r1, #0x4]
|
|
str r11, [r4, r10]
|
|
add r1, r1, #8
|
|
sub r8, r8, #1
|
|
cmp r8, #0
|
|
bgt update_calib
|
|
|
|
/* perform a force measurement. */
|
|
ldr r8, =0x800
|
|
str r8, [r4, #MMDC0_MPMUR0]
|
|
/* Wait for FRC_MSR to clear. */
|
|
1:
|
|
ldr r8, [r4, #MMDC0_MPMUR0]
|
|
and r8, r8, #0x800
|
|
cmp r8, #0x0
|
|
bne 1b
|
|
|
|
/* clear SBS - unblock DDR accesses. */
|
|
ldr r8, [r4, #MMDC0_MADPCR0]
|
|
bic r8, r8, #(1 << 8)
|
|
str r8, [r4, #MMDC0_MADPCR0]
|
|
|
|
mov r8, #0x0
|
|
str r8, [r4, #MMDC0_MDSCR]
|
|
poll_conreq_clear_2:
|
|
ldr r8, [r4, #MMDC0_MDSCR]
|
|
and r8, r8, #(0x4 << 12)
|
|
cmp r8, #(0x4 << 12)
|
|
beq poll_conreq_clear_2
|
|
|
|
done:
|
|
|
|
/* MMDC0_MAPSR adopt power down enable. */
|
|
ldr r8, [r4, #MMDC0_MAPSR]
|
|
bic r8, r8, #0x01
|
|
str r8, [r4, #MMDC0_MAPSR]
|
|
|
|
is_ca7
|
|
beq skip_enable_l2
|
|
|
|
#ifdef CONFIG_CACHE_L2X0
|
|
/* Unlock L2. */
|
|
ldr r8, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR)
|
|
ldr r9, [r8, #PL310_AUX_CTRL]
|
|
tst r9, #PL310_AUX_16WAY_BIT
|
|
mov r10, #PL310_LOCKDOWN_NBREGS
|
|
mov r9, #0x00 /* 8 ways mask */
|
|
orrne r9, #0x0000 /* 16 ways mask */
|
|
add r11, r8, #PL310_DCACHE_LOCKDOWN_BASE
|
|
1: /* lock Dcache and Icache */
|
|
str r9, [r11], #PL310_LOCKDOWN_SZREG
|
|
str r9, [r11], #PL310_LOCKDOWN_SZREG
|
|
subs r10, r10, #1
|
|
bne 1b
|
|
|
|
#endif
|
|
|
|
skip_enable_l2:
|
|
/* Enable L1 data cache. */
|
|
mrc p15, 0, r7, c1, c0, 0
|
|
orr r7, r7, #0x4
|
|
mcr p15, 0, r7, c1, c0, 0
|
|
|
|
/* Restore the TTBCR */
|
|
dsb
|
|
isb
|
|
|
|
/* Read TTBCR and set PD0=0, N = 0 */
|
|
mrc p15, 0, r6, c2, c0, 2
|
|
bic r6, r6, #0x11
|
|
mcr p15, 0, r6, c2, c0, 2
|
|
|
|
dsb
|
|
isb
|
|
|
|
/* flush the TLB */
|
|
ldr r6, =0x0
|
|
mcr p15, 0, r6, c8, c3, 0
|
|
|
|
dsb
|
|
isb
|
|
|
|
/* Enable Branch Prediction, Z bit in SCTLR. */
|
|
mrc p15, 0, r7, c1, c0, 0
|
|
orr r7, r7, #0x800
|
|
mcr p15, 0, r7, c1, c0, 0
|
|
|
|
/* Flush the Branch Target Address Cache (BTAC) */
|
|
ldr r7, =0x0
|
|
mcr p15, 0, r7, c7, c1, 6
|
|
|
|
/* restore registers */
|
|
ldmfd sp!, {r4 - r11}
|
|
mov pc, lr
|
|
|
|
/*
|
|
* Add ltorg here to ensure that all
|
|
* literals are stored here and are
|
|
* within the text space.
|
|
*/
|
|
.ltorg
|
|
imx6_up_ddr3_freq_change_end:
|
|
ENDPROC(imx6_up_ddr3_freq_change)
|