235 lines
6.3 KiB
C
235 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
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* Copyright 2017-2018 NXP.
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*/
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#include <linux/busfreq-imx.h>
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#include <linux/cpuidle.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_fdt.h>
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#include <linux/platform_device.h>
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#include <linux/psci.h>
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#include <linux/regulator/consumer.h>
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#include <linux/regulator/driver.h>
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#include <linux/regulator/machine.h>
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#include <asm/cpuidle.h>
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#include <asm/fncpy.h>
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#include <asm/proc-fns.h>
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#include <uapi/linux/psci.h>
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#include "common.h"
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#include "cpuidle.h"
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#include "hardware.h"
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#define MAX_MMDC_IO_NUM 19
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static void __iomem *wfi_iram_base;
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extern unsigned long iram_tlb_base_addr;
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#ifdef CONFIG_CPU_FREQ
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extern unsigned long mx6sl_lpm_wfi_start asm("mx6sl_lpm_wfi_start");
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extern unsigned long mx6sl_lpm_wfi_end asm("mx6sl_lpm_wfi_end");
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#endif
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struct imx6_cpuidle_pm_info {
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u32 pm_info_size; /* Size of pm_info */
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u32 ttbr;
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void __iomem *mmdc_base;
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void __iomem *iomuxc_base;
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void __iomem *ccm_base;
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void __iomem *l2_base;
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void __iomem *anatop_base;
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u32 mmdc_io_num; /*Number of MMDC IOs which need saved/restored. */
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u32 mmdc_io_val[MAX_MMDC_IO_NUM][2]; /* To save offset and value */
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} __aligned(8);
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static const u32 imx6sl_mmdc_io_offset[] __initconst = {
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0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
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0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
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0x300, 0x31c, 0x338, 0x5ac, /*CAS, RAS, SDCLK_0, GPR_ADDS */
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0x33c, 0x340, 0x5b0, 0x5c0, /*SODT0, SODT1, ,MODE_CTL, MODE */
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0x330, 0x334, 0x320, /*SDCKE0, SDCK1, RESET */
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};
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static struct regulator *vbus_ldo;
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static struct regulator_dev *ldo2p5_dummy_regulator_rdev;
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static struct regulator_init_data ldo2p5_dummy_initdata = {
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.constraints = {
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.valid_ops_mask = REGULATOR_CHANGE_STATUS,
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},
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};
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static int ldo2p5_dummy_enable;
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static void (*imx6sl_wfi_in_iram_fn)(void __iomem *iram_vbase,
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int audio_mode, bool vbus_ldo);
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#define MX6SL_POWERDWN_IDLE_PARAM \
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((1 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \
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(1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \
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(PSCI_POWER_STATE_TYPE_POWER_DOWN << PSCI_0_2_POWER_STATE_TYPE_SHIFT))
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static int imx6sl_enter_wait(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index)
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{
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int mode = get_bus_freq_mode();
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imx6_set_lpm(WAIT_UNCLOCKED);
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if ((mode == BUS_FREQ_AUDIO) || (mode == BUS_FREQ_ULTRA_LOW)) {
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/*
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* bit 2 used for low power mode;
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* bit 1 used for the ldo2p5_dummmy enable
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*/
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if (psci_ops.cpu_suspend) {
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psci_ops.cpu_suspend((MX6SL_POWERDWN_IDLE_PARAM | ((mode == BUS_FREQ_AUDIO ? 1 : 0) << 2) |
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(ldo2p5_dummy_enable ? 1 : 0) << 1), __pa(cpu_resume));
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} else {
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imx6sl_wfi_in_iram_fn(wfi_iram_base, (mode == BUS_FREQ_AUDIO) ? 1 : 0,
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ldo2p5_dummy_enable);
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}
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} else {
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/*
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* Software workaround for ERR005311, see function
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* description for details.
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*/
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imx6sl_set_wait_clk(true);
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cpu_do_idle();
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imx6sl_set_wait_clk(false);
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}
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imx6_set_lpm(WAIT_CLOCKED);
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return index;
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}
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static struct cpuidle_driver imx6sl_cpuidle_driver = {
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.name = "imx6sl_cpuidle",
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.owner = THIS_MODULE,
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.states = {
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/* WFI */
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ARM_CPUIDLE_WFI_STATE,
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/* WAIT */
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{
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.exit_latency = 50,
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.target_residency = 75,
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.flags = CPUIDLE_FLAG_TIMER_STOP,
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.enter = imx6sl_enter_wait,
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.name = "WAIT",
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.desc = "Clock off",
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},
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},
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.state_count = 2,
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.safe_state_index = 0,
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};
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int __init imx6sl_cpuidle_init(void)
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{
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#ifdef CONFIG_CPU_FREQ
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struct imx6_cpuidle_pm_info *pm_info;
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int i;
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const u32 *mmdc_offset_array;
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u32 wfi_code_size;
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vbus_ldo = regulator_get(NULL, "ldo2p5-dummy");
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if (IS_ERR(vbus_ldo))
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vbus_ldo = NULL;
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wfi_iram_base = (void *)(iram_tlb_base_addr + MX6_CPUIDLE_IRAM_ADDR_OFFSET);
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/* Make sure wif_iram_base is 8 byte aligned. */
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if ((uintptr_t)(wfi_iram_base) & (FNCPY_ALIGN - 1))
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wfi_iram_base += FNCPY_ALIGN - ((uintptr_t)wfi_iram_base % (FNCPY_ALIGN));
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pm_info = wfi_iram_base;
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pm_info->pm_info_size = sizeof(*pm_info);
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pm_info->mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset);
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mmdc_offset_array = imx6sl_mmdc_io_offset;
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pm_info->mmdc_base = (void __iomem *)IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR);
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pm_info->ccm_base = (void __iomem *)IMX_IO_P2V(MX6Q_CCM_BASE_ADDR);
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pm_info->anatop_base = (void __iomem *)IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR);
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pm_info->iomuxc_base = (void __iomem *)IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR);
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pm_info->l2_base = (void __iomem *)IMX_IO_P2V(MX6Q_L2_BASE_ADDR);
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/* Only save mmdc io offset, settings will be saved in asm code */
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for (i = 0; i < pm_info->mmdc_io_num; i++)
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pm_info->mmdc_io_val[i][0] = mmdc_offset_array[i];
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/* calculate the wfi code size */
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wfi_code_size = (&mx6sl_lpm_wfi_end -&mx6sl_lpm_wfi_start) *4;
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imx6sl_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base + sizeof(*pm_info),
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&imx6sl_low_power_idle, wfi_code_size);
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#endif
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return cpuidle_register(&imx6sl_cpuidle_driver, NULL);
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}
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static int imx_ldo2p5_dummy_enable(struct regulator_dev *rdev)
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{
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ldo2p5_dummy_enable = 1;
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return 0;
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}
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static int imx_ldo2p5_dummy_disable(struct regulator_dev *rdev)
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{
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ldo2p5_dummy_enable = 0;
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return 0;
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}
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static int imx_ldo2p5_dummy_is_enable(struct regulator_dev *rdev)
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{
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return ldo2p5_dummy_enable;
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}
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static struct regulator_ops ldo2p5_dummy_ops = {
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.enable = imx_ldo2p5_dummy_enable,
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.disable = imx_ldo2p5_dummy_disable,
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.is_enabled = imx_ldo2p5_dummy_is_enable,
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};
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static struct regulator_desc ldo2p5_dummy_desc = {
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.name = "ldo2p5-dummy",
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.id = -1,
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.type = REGULATOR_VOLTAGE,
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.owner = THIS_MODULE,
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.ops = &ldo2p5_dummy_ops,
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};
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static int ldo2p5_dummy_probe(struct platform_device *pdev)
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{
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struct regulator_config config = { };
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int ret;
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config.dev = &pdev->dev;
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config.init_data = &ldo2p5_dummy_initdata;
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config.of_node = pdev->dev.of_node;
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ldo2p5_dummy_regulator_rdev = regulator_register(&ldo2p5_dummy_desc, &config);
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if (IS_ERR(ldo2p5_dummy_regulator_rdev)) {
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ret = PTR_ERR(ldo2p5_dummy_regulator_rdev);
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dev_err(&pdev->dev, "Failed to register dummy ldo2p5 regulator: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static const struct of_device_id imx_ldo2p5_dummy_ids[] = {
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{ .compatible = "fsl,imx6-dummy-ldo2p5", },
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{ },
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};
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MODULE_DEVICE_TABLE(ofm, imx_ldo2p5_dummy_ids);
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static struct platform_driver ldo2p5_dummy_driver = {
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.probe = ldo2p5_dummy_probe,
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.driver = {
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.name = "ldo2p5-dummy",
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.owner = THIS_MODULE,
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.of_match_table = imx_ldo2p5_dummy_ids,
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},
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};
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module_platform_driver(ldo2p5_dummy_driver);
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