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72cd4064fc
ARMv8M introduces support for Security extension to M class, among other things it affects exception handling, especially, encoding of EXC_RETURN. The new bits have been added: Bit [6] Secure or Non-secure stack Bit [5] Default callee register stacking Bit [0] Exception Secure which conflicts with hard-coded value of EXC_RETURN: In fact, we only care of few bits: Bit [3] Mode (0 - Handler, 1 - Thread) Bit [2] Stack pointer selection (0 - Main, 1 - Process) We can toggle only those bits and left other bits as they were on exception entry. It is basically, what patch does - saves EXC_RETURN when we do transition form Thread to Handler mode (it is first svc), so later saved value is used instead of EXC_RET_THREADMODE_PROCESSSTACK. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
98 lines
3.2 KiB
C
98 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Common defines for v7m cpus
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*/
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#define V7M_SCS_ICTR IOMEM(0xe000e004)
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#define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f
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#define BASEADDR_V7M_SCB IOMEM(0xe000ed00)
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#define V7M_SCB_CPUID 0x00
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#define V7M_SCB_ICSR 0x04
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#define V7M_SCB_ICSR_PENDSVSET (1 << 28)
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#define V7M_SCB_ICSR_PENDSVCLR (1 << 27)
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#define V7M_SCB_ICSR_RETTOBASE (1 << 11)
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#define V7M_SCB_VTOR 0x08
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#define V7M_SCB_AIRCR 0x0c
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#define V7M_SCB_AIRCR_VECTKEY (0x05fa << 16)
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#define V7M_SCB_AIRCR_SYSRESETREQ (1 << 2)
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#define V7M_SCB_SCR 0x10
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#define V7M_SCB_SCR_SLEEPDEEP (1 << 2)
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#define V7M_SCB_CCR 0x14
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#define V7M_SCB_CCR_STKALIGN (1 << 9)
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#define V7M_SCB_CCR_DC (1 << 16)
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#define V7M_SCB_CCR_IC (1 << 17)
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#define V7M_SCB_CCR_BP (1 << 18)
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#define V7M_SCB_SHPR2 0x1c
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#define V7M_SCB_SHPR3 0x20
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#define V7M_SCB_SHCSR 0x24
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#define V7M_SCB_SHCSR_USGFAULTENA (1 << 18)
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#define V7M_SCB_SHCSR_BUSFAULTENA (1 << 17)
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#define V7M_SCB_SHCSR_MEMFAULTENA (1 << 16)
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#define V7M_xPSR_FRAMEPTRALIGN 0x00000200
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#define V7M_xPSR_EXCEPTIONNO 0x000001ff
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/*
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* When branching to an address that has bits [31:28] == 0xf an exception return
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* occurs. Bits [27:5] are reserved (SBOP). If the processor implements the FP
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* extension Bit [4] defines if the exception frame has space allocated for FP
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* state information, SBOP otherwise. Bit [3] defines the mode that is returned
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* to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used
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* (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
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*/
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#define EXC_RET_STACK_MASK 0x00000004
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#define EXC_RET_THREADMODE_PROCESSSTACK (3 << 2)
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/* Cache related definitions */
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#define V7M_SCB_CLIDR 0x78 /* Cache Level ID register */
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#define V7M_SCB_CTR 0x7c /* Cache Type register */
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#define V7M_SCB_CCSIDR 0x80 /* Cache size ID register */
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#define V7M_SCB_CSSELR 0x84 /* Cache size selection register */
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/* Memory-mapped MPU registers for M-class */
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#define MPU_TYPE 0x90
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#define MPU_CTRL 0x94
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#define MPU_CTRL_ENABLE 1
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#define MPU_CTRL_PRIVDEFENA (1 << 2)
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#define PMSAv7_RNR 0x98
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#define PMSAv7_RBAR 0x9c
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#define PMSAv7_RASR 0xa0
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#define PMSAv8_RNR 0x98
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#define PMSAv8_RBAR 0x9c
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#define PMSAv8_RLAR 0xa0
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#define PMSAv8_RBAR_A(n) (PMSAv8_RBAR + 8*(n))
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#define PMSAv8_RLAR_A(n) (PMSAv8_RLAR + 8*(n))
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#define PMSAv8_MAIR0 0xc0
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#define PMSAv8_MAIR1 0xc4
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/* Cache opeartions */
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#define V7M_SCB_ICIALLU 0x250 /* I-cache invalidate all to PoU */
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#define V7M_SCB_ICIMVAU 0x258 /* I-cache invalidate by MVA to PoU */
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#define V7M_SCB_DCIMVAC 0x25c /* D-cache invalidate by MVA to PoC */
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#define V7M_SCB_DCISW 0x260 /* D-cache invalidate by set-way */
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#define V7M_SCB_DCCMVAU 0x264 /* D-cache clean by MVA to PoU */
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#define V7M_SCB_DCCMVAC 0x268 /* D-cache clean by MVA to PoC */
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#define V7M_SCB_DCCSW 0x26c /* D-cache clean by set-way */
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#define V7M_SCB_DCCIMVAC 0x270 /* D-cache clean and invalidate by MVA to PoC */
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#define V7M_SCB_DCCISW 0x274 /* D-cache clean and invalidate by set-way */
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#define V7M_SCB_BPIALL 0x278 /* D-cache clean and invalidate by set-way */
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#ifndef __ASSEMBLY__
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enum reboot_mode;
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void armv7m_restart(enum reboot_mode mode, const char *cmd);
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#endif /* __ASSEMBLY__ */
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