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6f002c57c7
Lichee zero plus is a core board made by Sipeed, which includes on-board TF slot or SMT SD NAND, and optional SPI NOR or eMMC, a UART debug header, a microUSB slot and a gold finger connector for expansion. It can use either Sochip S3 or Allwinner S3L SoC. Add the basic device tree for the core board, w/o optional onboard storage, and with S3 SoC. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
54 lines
881 B
Plaintext
54 lines
881 B
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
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*/
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/dts-v1/;
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#include "sun8i-v3.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Sipeed Lichee Zero Plus";
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compatible = "sipeed,lichee-zero-plus", "sochip,s3",
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"allwinner,sun8i-v3";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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reg_vcc3v3: vcc3v3 {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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&mmc0 {
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broken-cd;
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bus-width = <4>;
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vmmc-supply = <®_vcc3v3>;
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status = "okay";
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};
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&uart0 {
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pinctrl-0 = <&uart0_pb_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&usb_otg {
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dr_mode = "peripheral";
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status = "okay";
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};
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&usbphy {
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usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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