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d85b2ad35a
This is like commit0ca87bd5ba("ARM: dts: rockchip: Add pin names for rk3288-veyron-jerry") and commitca3516b32c("ARM: dts: rockchip: Add pin names for rk3288-veyron-minnie") but for 3 more veyron boards. A few notes: - While there is most certainly duplication between all the veyron boards, it still feels like it is sane to just have each board have a full list of its pin names. The format of "gpio-line-names" does not lend itself to one-off overriding and besides it seems sane to more fully match schematic names. Also note that the extra duplication here is only in source code and is unlikely to ever change (since these boards are shipped). Duplication in the .dtb files is unavoidable. - veyron-jaq and veyron-mighty are very closely related and so I have shared a single list for them both with comments on how they are different. This is just a typo fix on one of the boards, a possible missing signal on one of the boards (or perhaps I was never given the most recent schematics?) and dealing with the fact that one of the two boards has full sized SD. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
438 lines
8.8 KiB
Plaintext
438 lines
8.8 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Google Veyron Mickey Rev 0 board device tree source
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*
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* Copyright 2015 Google, Inc
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*/
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/dts-v1/;
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#include "rk3288-veyron.dtsi"
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/ {
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model = "Google Mickey";
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compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7",
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"google,veyron-mickey-rev6", "google,veyron-mickey-rev5",
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"google,veyron-mickey-rev4", "google,veyron-mickey-rev3",
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"google,veyron-mickey-rev2", "google,veyron-mickey-rev1",
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"google,veyron-mickey-rev0", "google,veyron-mickey",
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"google,veyron", "rockchip,rk3288";
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vcc_5v: vcc-5v {
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vin-supply = <&vcc33_sys>;
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};
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vcc33_io: vcc33_io {
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compatible = "regulator-fixed";
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regulator-name = "vcc33_io";
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regulator-always-on;
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regulator-boot-on;
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vin-supply = <&vcc33_sys>;
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};
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};
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&cpu_thermal {
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/delete-node/ trips;
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/delete-node/ cooling-maps;
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trips {
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cpu_alert_almost_warm: cpu_alert_almost_warm {
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temperature = <63000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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cpu_alert_warm: cpu_alert_warm {
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temperature = <65000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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cpu_alert_almost_hot: cpu_alert_almost_hot {
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temperature = <80000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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cpu_alert_hot: cpu_alert_hot {
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temperature = <82000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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cpu_alert_hotter: cpu_alert_hotter {
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temperature = <84000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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cpu_alert_very_hot: cpu_alert_very_hot {
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temperature = <85000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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cpu_crit: cpu_crit {
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temperature = <90000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "critical";
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};
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};
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cooling-maps {
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/*
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* After 1st level, throttle the CPU down to as low as 1.4 GHz
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* and don't let the GPU go faster than 400 MHz.
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*/
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cpu_warm_limit_cpu {
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trip = <&cpu_alert_warm>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT 4>,
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<&cpu1 THERMAL_NO_LIMIT 4>,
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<&cpu2 THERMAL_NO_LIMIT 4>,
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<&cpu3 THERMAL_NO_LIMIT 4>;
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};
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cpu_warm_limit_gpu {
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trip = <&cpu_alert_warm>;
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cooling-device = <&gpu 1 1>;
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};
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/*
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* Add some discrete steps to help throttling system deal
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* with the fact that there are two passive cooling devices:
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* the CPU and the GPU.
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*
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* - 1.2 GHz - 1.0 GHz (almost hot)
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* - 800 MHz (hot)
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* - 800 MHz - 696 MHz (hotter)
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* - 696 MHz - min (very hot)
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*
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* Note:
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* - 800 MHz appears to be a "sweet spot" for me. I can run
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* some pretty serious workload here and be happy.
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* - After 696 MHz we stop lowering voltage, so throttling
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* past there is less effective.
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*/
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cpu_almost_hot_limit_cpu {
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trip = <&cpu_alert_almost_hot>;
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cooling-device = <&cpu0 5 6>, <&cpu1 5 6>, <&cpu2 5 6>,
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<&cpu3 5 6>;
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};
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cpu_hot_limit_cpu {
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trip = <&cpu_alert_hot>;
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cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, <&cpu2 7 7>,
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<&cpu3 7 7>;
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};
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cpu_hotter_limit_cpu {
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trip = <&cpu_alert_hotter>;
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cooling-device = <&cpu0 7 8>, <&cpu1 7 8>, <&cpu2 7 8>,
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<&cpu3 7 8>;
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};
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cpu_very_hot_limit_cpu {
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trip = <&cpu_alert_very_hot>;
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cooling-device = <&cpu0 8 THERMAL_NO_LIMIT>,
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<&cpu1 8 THERMAL_NO_LIMIT>,
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<&cpu2 8 THERMAL_NO_LIMIT>,
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<&cpu3 8 THERMAL_NO_LIMIT>;
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};
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/* At very hot, don't let GPU go over 300 MHz */
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cpu_very_hot_limit_gpu {
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trip = <&cpu_alert_very_hot>;
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cooling-device = <&gpu 2 2>;
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};
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};
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};
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&gpu_thermal {
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/delete-node/ trips;
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/delete-node/ cooling-maps;
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trips {
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gpu_alert_warmish: gpu_alert_warmish {
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temperature = <60000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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gpu_alert_warm: gpu_alert_warm {
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temperature = <65000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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gpu_alert_hotter: gpu_alert_hotter {
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temperature = <84000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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gpu_alert_very_very_hot: gpu_alert_very_very_hot {
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temperature = <86000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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gpu_crit: gpu_crit {
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temperature = <90000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "critical";
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};
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};
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cooling-maps {
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/* After 1st level throttle the GPU down to as low as 400 MHz */
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gpu_warmish_limit_gpu {
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trip = <&gpu_alert_warmish>;
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cooling-device = <&gpu THERMAL_NO_LIMIT 1>;
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};
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/*
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* Slightly after we throttle the GPU, we'll also make sure that
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* the CPU can't go faster than 1.4 GHz. Note that we won't
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* throttle the CPU lower than 1.4 GHz due to GPU heat--we'll
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* let the CPU do the rest itself.
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*/
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gpu_warm_limit_cpu {
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trip = <&gpu_alert_warm>;
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cooling-device = <&cpu0 4 4>,
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<&cpu1 4 4>,
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<&cpu2 4 4>,
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<&cpu3 4 4>;
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};
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/* When hot, GPU goes down to 300 MHz */
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gpu_hotter_limit_gpu {
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trip = <&gpu_alert_hotter>;
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cooling-device = <&gpu 2 2>;
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};
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/* When really hot, don't let GPU go _above_ 300 MHz */
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gpu_very_very_hot_limit_gpu {
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trip = <&gpu_alert_very_very_hot>;
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cooling-device = <&gpu 2 THERMAL_NO_LIMIT>;
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};
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};
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};
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&i2c2 {
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status = "disabled";
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};
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&i2c4 {
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status = "disabled";
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};
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&i2s {
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status = "okay";
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};
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&rk808 {
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pinctrl-names = "default";
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pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
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dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
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<&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
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/delete-property/ vcc6-supply;
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/delete-property/ vcc12-supply;
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vcc11-supply = <&vcc33_sys>;
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regulators {
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/* vcc33_io is sourced directly from vcc33_sys */
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/delete-node/ LDO_REG1;
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/delete-node/ LDO_REG7;
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/* This is not a pwren anymore, but the real power supply */
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vdd10_lcd: LDO_REG7 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-name = "vdd10_lcd";
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regulator-suspend-mem-disabled;
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};
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vcc18_lcd: LDO_REG8 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-name = "vcc18_lcd";
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regulator-suspend-mem-disabled;
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};
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};
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};
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&gpio0 {
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gpio-line-names = "PMIC_SLEEP_AP",
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"",
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"",
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"",
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"PMIC_INT_L",
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"POWER_BUTTON_L",
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"",
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"",
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"",
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/*
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* RECOVERY_SW_L is Chrome OS ABI. Schematics call
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* it REC_MODE_L.
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*/
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"RECOVERY_SW_L",
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"OT_RESET",
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"",
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"",
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"AP_WARM_RESET_H",
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"",
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"I2C0_SDA_PMIC",
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"I2C0_SCL_PMIC",
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"",
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"nFALUT";
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};
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&gpio2 {
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gpio-line-names = "CONFIG0",
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"CONFIG1",
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"CONFIG2",
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"",
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"",
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"",
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"",
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"CONFIG3",
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"",
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"EMMC_RST_L";
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};
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&gpio3 {
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gpio-line-names = "FLASH0_D0",
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"FLASH0_D1",
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"FLASH0_D2",
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"FLASH0_D3",
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"FLASH0_D4",
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"FLASH0_D5",
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"FLASH0_D6",
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"FLASH0_D7",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"FLASH0_CS2/EMMC_CMD",
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"",
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"FLASH0_DQS/EMMC_CLKO";
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};
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&gpio4 {
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gpio-line-names = "",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"UART0_RXD",
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"UART0_TXD",
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"UART0_CTS_L",
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"UART0_RTS_L",
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"SDIO0_D0",
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"SDIO0_D1",
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"SDIO0_D2",
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"SDIO0_D3",
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"SDIO0_CMD",
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"SDIO0_CLK",
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"BT_DEV_WAKE",
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"",
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"WIFI_ENABLE_H",
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"BT_ENABLE_L",
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"WIFI_HOST_WAKE",
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"BT_HOST_WAKE";
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};
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&gpio7 {
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gpio-line-names = "",
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"PWM_LOG",
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"",
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"",
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"TPM_INT_H",
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"SDMMC_DET_L",
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/*
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* AP_FLASH_WP_L is Chrome OS ABI. Schematics call
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* it FW_WP_AP.
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*/
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"AP_FLASH_WP_L",
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"",
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"CPU_NMI",
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"DVSOK",
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"HDMI_WAKE",
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"POWER_HDMI_ON",
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"DVS1",
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"",
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"",
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"DVS2",
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"HDMI_CEC",
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"",
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"",
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"I2C5_SDA_HDMI",
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"I2C5_SCL_HDMI",
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"",
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"UART2_RXD",
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"UART2_TXD";
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};
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&gpio8 {
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gpio-line-names = "RAM_ID0",
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"RAM_ID1",
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"RAM_ID2",
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"RAM_ID3",
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"I2C1_SDA_TPM",
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"I2C1_SCL_TPM",
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"SPI2_CLK",
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"SPI2_CS0",
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"SPI2_RXD",
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"SPI2_TXD";
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};
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&pinctrl {
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hdmi {
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power_hdmi_on: power-hdmi-on {
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rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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pmic {
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dvs_1: dvs-1 {
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rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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dvs_2: dvs-2 {
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rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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};
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};
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&usb_host0_ehci {
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status = "disabled";
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};
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&usb_host1 {
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status = "disabled";
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};
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&vcc50_hdmi {
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enable-active-high;
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gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&power_hdmi_on>;
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};
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