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1fae0ad1e2
The AHB queue manager and Network Processing Engines are present on all IXP4xx SoCs, so we add them to the overarching device tree include. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
70 lines
1.7 KiB
Plaintext
70 lines
1.7 KiB
Plaintext
// SPDX-License-Identifier: ISC
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/*
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* Device Tree file for Intel XScale Network Processors
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* in the IXP 4xx series.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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interrupt-parent = <&intcon>;
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qmgr: queue-manager@60000000 {
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compatible = "intel,ixp4xx-ahb-queue-manager";
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reg = <0x60000000 0x4000>;
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interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
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};
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uart0: serial@c8000000 {
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compatible = "intel,xscale-uart";
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reg = <0xc8000000 0x1000>;
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/*
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* The reg-offset and reg-shift is a side effect
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* of running the platform in big endian mode.
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*/
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reg-offset = <3>;
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reg-shift = <2>;
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interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <14745600>;
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no-loopback-test;
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};
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gpio0: gpio@c8004000 {
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compatible = "intel,ixp4xx-gpio";
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reg = <0xc8004000 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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intcon: interrupt-controller@c8003000 {
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/*
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* Note: no compatible string. The subvariant of the
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* chip needs to define what version it is. The
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* location of the interrupt controller is fixed in
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* memory across all variants.
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*/
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reg = <0xc8003000 0x100>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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timer@c8005000 {
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compatible = "intel,ixp4xx-timer";
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reg = <0xc8005000 0x100>;
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interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
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};
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npe@c8006000 {
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compatible = "intel,ixp4xx-network-processing-engine";
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reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
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};
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};
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};
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