138 lines
4.0 KiB
Plaintext
138 lines
4.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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//
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// Copyright 2016 Freescale Semiconductor, Inc.
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#include "imx6ul.dtsi"
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#include "imx6ull-pinfunc.h"
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#include "imx6ull-pinfunc-snvs.h"
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/* Delete UART8 in AIPS-1 (i.MX6UL specific) */
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/delete-node/ &uart8;
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/* Delete CAAM node in AIPS-2 (i.MX6UL specific) */
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/delete-node/ &crypto;
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&cpu0 {
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clock-frequency = <900000000>;
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fsl,low-power-run;
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operating-points = <
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/* kHz uV */
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900000 1275000
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792000 1225000
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528000 1175000
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396000 1025000
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198000 950000
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>;
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fsl,soc-operating-points = <
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/* KHz uV */
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900000 1250000
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792000 1175000
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528000 1175000
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396000 1175000
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198000 1175000
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>;
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};
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&ocotp {
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compatible = "fsl,imx6ull-ocotp", "syscon";
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};
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&pxp {
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compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma";
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_PXP>;
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clock-names = "pxp_ipg", "pxp_axi";
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status = "disabled";
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};
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&usdhc1 {
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compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc";
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assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
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assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
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assigned-clock-rates = <0>, <132000000>;
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};
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&usdhc2 {
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compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc";
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assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
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assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
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assigned-clock-rates = <0>, <132000000>;
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};
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/ {
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soc {
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busfreq {
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compatible = "fsl,imx_busfreq";
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clocks = <&clks IMX6UL_CLK_PLL2_PFD2>, <&clks IMX6UL_CLK_PLL2_198M>,
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<&clks IMX6UL_CLK_PLL2_BUS>, <&clks IMX6UL_CLK_ARM>,
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<&clks IMX6UL_CLK_PLL3_USB_OTG>, <&clks IMX6UL_CLK_PERIPH>,
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<&clks IMX6UL_CLK_PERIPH_PRE>, <&clks IMX6UL_CLK_PERIPH_CLK2>,
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<&clks IMX6UL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6UL_CLK_OSC>,
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<&clks IMX6UL_CLK_AHB>, <&clks IMX6UL_CLK_AXI>,
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<&clks IMX6UL_CLK_PERIPH2>, <&clks IMX6UL_CLK_PERIPH2_PRE>,
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<&clks IMX6UL_CLK_PERIPH2_CLK2>, <&clks IMX6UL_CLK_PERIPH2_CLK2_SEL>,
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<&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_MMDC_P0_FAST>, <&clks IMX6UL_PLL1_BYPASS_SRC>,
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<&clks IMX6UL_PLL1_BYPASS>, <&clks IMX6UL_CLK_PLL1_SYS>, <&clks IMX6UL_CLK_PLL1_SW>,
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<&clks IMX6UL_CLK_PLL1>;
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clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg",
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"periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc",
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"ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel",
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"step", "mmdc", "pll1_bypass_src", "pll1_bypass", "pll1_sys", "pll1_sw", "pll1";
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fsl,max_ddr_freq = <400000000>;
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};
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aips3: aips-bus@2200000 {
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x02200000 0x100000>;
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ranges;
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dcp: crypto@2280000 {
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compatible = "fsl,imx6ull-dcp", "fsl,imx28-dcp";
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reg = <0x02280000 0x4000>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6ULL_CLK_DCP_CLK>;
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clock-names = "dcp";
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};
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rngb: rng@2284000 {
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compatible = "fsl,imx25-rngb";
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reg = <0x02284000 0x4000>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_DUMMY>;
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};
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iomuxc_snvs: iomuxc-snvs@2290000 {
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compatible = "fsl,imx6ull-iomuxc-snvs";
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reg = <0x02290000 0x4000>;
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};
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uart8: serial@2288000 {
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compatible = "fsl,imx6ul-uart",
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"fsl,imx6q-uart";
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reg = <0x02288000 0x4000>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_UART8_IPG>,
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<&clks IMX6UL_CLK_UART8_SERIAL>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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epdc: epdc@228c000 {
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compatible = "fsl,imx7d-epdc";
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x228c000 0x4000>;
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clocks = <&clks IMX6ULL_CLK_EPDC_ACLK>,
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<&clks IMX6ULL_CLK_EPDC_PIX>;
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clock-names = "epdc_axi", "epdc_pix";
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/* Need to fix epdc-ram */
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/* epdc-ram = <&gpr 0x4 30>; */
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status = "disabled";
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};
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};
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};
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};
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