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9952f6918d
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
162 lines
3.1 KiB
Plaintext
162 lines
3.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright 2011-2012 Calxeda, Inc.
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*/
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/dts-v1/;
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/* First 4KB has pen for secondary cores. */
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/memreserve/ 0x00000000 0x0001000;
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/ {
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model = "Calxeda Highbank";
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compatible = "calxeda,highbank";
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#address-cells = <1>;
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#size-cells = <1>;
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clock-ranges;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@900 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0x900>;
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next-level-cache = <&L2>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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operating-points = <
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/* kHz ignored */
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1300000 1000000
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1200000 1000000
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1100000 1000000
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800000 1000000
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400000 1000000
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200000 1000000
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>;
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clock-latency = <100000>;
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};
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cpu@901 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0x901>;
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next-level-cache = <&L2>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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operating-points = <
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/* kHz ignored */
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1300000 1000000
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1200000 1000000
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1100000 1000000
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800000 1000000
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400000 1000000
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200000 1000000
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>;
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clock-latency = <100000>;
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};
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cpu@902 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0x902>;
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next-level-cache = <&L2>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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operating-points = <
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/* kHz ignored */
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1300000 1000000
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1200000 1000000
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1100000 1000000
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800000 1000000
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400000 1000000
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200000 1000000
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>;
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clock-latency = <100000>;
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};
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cpu@903 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0x903>;
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next-level-cache = <&L2>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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operating-points = <
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/* kHz ignored */
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1300000 1000000
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1200000 1000000
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1100000 1000000
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800000 1000000
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400000 1000000
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200000 1000000
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>;
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clock-latency = <100000>;
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};
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};
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memory {
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name = "memory";
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device_type = "memory";
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reg = <0x00000000 0xff900000>;
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};
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soc {
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ranges = <0x00000000 0x00000000 0xffffffff>;
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memory-controller@fff00000 {
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compatible = "calxeda,hb-ddr-ctrl";
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reg = <0xfff00000 0x1000>;
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interrupts = <0 91 4>;
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};
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timer@fff10600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xfff10600 0x20>;
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interrupts = <1 13 0xf01>;
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clocks = <&a9periphclk>;
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};
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watchdog@fff10620 {
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compatible = "arm,cortex-a9-twd-wdt";
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reg = <0xfff10620 0x20>;
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interrupts = <1 14 0xf01>;
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clocks = <&a9periphclk>;
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};
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intc: interrupt-controller@fff11000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#size-cells = <0>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0xfff11000 0x1000>,
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<0xfff10100 0x100>;
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};
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L2: l2-cache {
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compatible = "arm,pl310-cache";
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reg = <0xfff12000 0x1000>;
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interrupts = <0 70 4>;
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cache-unified;
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cache-level = <2>;
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
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};
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sregs@fff3c200 {
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compatible = "calxeda,hb-sregs-l2-ecc";
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reg = <0xfff3c200 0x100>;
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interrupts = <0 71 4 0 72 4>;
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};
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};
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};
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/include/ "ecx-common.dtsi"
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