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Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details the full gnu general public license is included in this distribution in the file called copying this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope [that] it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details the full gnu general public license is included in this distribution in the file called copying extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 57 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141901.515993066@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
139 lines
2.8 KiB
C
139 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright(c) 2015 EZchip Technologies.
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*/
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#include <linux/smp.h>
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#include <linux/of_fdt.h>
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#include <linux/io.h>
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#include <linux/irqdomain.h>
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#include <asm/irq.h>
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#include <plat/ctop.h>
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#include <plat/smp.h>
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#include <plat/mtm.h>
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#define NPS_DEFAULT_MSID 0x34
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#define NPS_MTM_CPU_CFG 0x90
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static char smp_cpuinfo_buf[128] = {"Extn [EZNPS-SMP]\t: On\n"};
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/* Get cpu map from device tree */
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static int __init eznps_get_map(const char *name, struct cpumask *cpumask)
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{
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unsigned long dt_root = of_get_flat_dt_root();
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const char *buf;
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buf = of_get_flat_dt_prop(dt_root, name, NULL);
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if (!buf)
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return 1;
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cpulist_parse(buf, cpumask);
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return 0;
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}
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/* Update board cpu maps */
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static void __init eznps_init_cpumasks(void)
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{
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struct cpumask cpumask;
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if (eznps_get_map("present-cpus", &cpumask)) {
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pr_err("Failed to get present-cpus from dtb");
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return;
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}
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init_cpu_present(&cpumask);
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if (eznps_get_map("possible-cpus", &cpumask)) {
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pr_err("Failed to get possible-cpus from dtb");
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return;
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}
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init_cpu_possible(&cpumask);
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}
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static void eznps_init_core(unsigned int cpu)
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{
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u32 sync_value;
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struct nps_host_reg_aux_hw_comply hw_comply;
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struct nps_host_reg_aux_lpc lpc;
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if (NPS_CPU_TO_THREAD_NUM(cpu) != 0)
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return;
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hw_comply.value = read_aux_reg(CTOP_AUX_HW_COMPLY);
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hw_comply.me = 1;
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hw_comply.le = 1;
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hw_comply.te = 1;
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write_aux_reg(CTOP_AUX_HW_COMPLY, hw_comply.value);
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/* Enable MMU clock */
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lpc.mep = 1;
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write_aux_reg(CTOP_AUX_LPC, lpc.value);
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/* Boot CPU only */
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if (!cpu) {
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/* Write to general purpose register in CRG */
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sync_value = ioread32be(REG_GEN_PURP_0);
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sync_value |= NPS_CRG_SYNC_BIT;
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iowrite32be(sync_value, REG_GEN_PURP_0);
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}
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}
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/*
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* Master kick starting another CPU
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*/
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static void __init eznps_smp_wakeup_cpu(int cpu, unsigned long pc)
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{
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struct nps_host_reg_mtm_cpu_cfg cpu_cfg;
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if (mtm_enable_thread(cpu) == 0)
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return;
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/* set PC, dmsid, and start CPU */
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cpu_cfg.value = (u32)res_service;
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cpu_cfg.dmsid = NPS_DEFAULT_MSID;
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cpu_cfg.cs = 1;
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iowrite32be(cpu_cfg.value, nps_mtm_reg_addr(cpu, NPS_MTM_CPU_CFG));
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}
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static void eznps_ipi_send(int cpu)
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{
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struct global_id gid;
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struct {
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union {
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struct {
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u32 num:8, cluster:8, core:8, thread:8;
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};
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u32 value;
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};
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} ipi;
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gid.value = cpu;
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ipi.thread = get_thread(gid);
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ipi.core = gid.core;
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ipi.cluster = nps_cluster_logic_to_phys(gid.cluster);
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ipi.num = NPS_IPI_IRQ;
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__asm__ __volatile__(
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" mov r3, %0\n"
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" .word %1\n"
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:
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: "r"(ipi.value), "i"(CTOP_INST_ASRI_0_R3)
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: "r3");
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}
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static void eznps_init_per_cpu(int cpu)
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{
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smp_ipi_irq_setup(cpu, NPS_IPI_IRQ);
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eznps_init_core(cpu);
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mtm_enable_core(cpu);
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}
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struct plat_smp_ops plat_smp_ops = {
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.info = smp_cpuinfo_buf,
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.init_early_smp = eznps_init_cpumasks,
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.cpu_kick = eznps_smp_wakeup_cpu,
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.ipi_send = eznps_ipi_send,
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.init_per_cpu = eznps_init_per_cpu,
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};
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