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0203fdc160
As a step towards making the atomic64 API use consistent types treewide, let's have the alpha atomic64 implementation use s64 as the underlying type for atomic64_t, rather than long, matching the generated headers. As atomic64_read() depends on the generic defintion of atomic64_t, this still returns long. This will be converted in a subsequent patch. Otherwise, there should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Matt Turner <mattst88@gmail.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Richard Henderson <rth@twiddle.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Will Deacon <will.deacon@arm.com> Cc: aou@eecs.berkeley.edu Cc: arnd@arndb.de Cc: bp@alien8.de Cc: catalin.marinas@arm.com Cc: davem@davemloft.net Cc: fenghua.yu@intel.com Cc: heiko.carstens@de.ibm.com Cc: herbert@gondor.apana.org.au Cc: jhogan@kernel.org Cc: linux@armlinux.org.uk Cc: mpe@ellerman.id.au Cc: palmer@sifive.com Cc: paul.burton@mips.com Cc: paulus@samba.org Cc: ralf@linux-mips.org Cc: tony.luck@intel.com Cc: vgupta@synopsys.com Link: https://lkml.kernel.org/r/20190522132250.26499-5-mark.rutland@arm.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
302 lines
8.3 KiB
C
302 lines
8.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ALPHA_ATOMIC_H
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#define _ALPHA_ATOMIC_H
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#include <linux/types.h>
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#include <asm/barrier.h>
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#include <asm/cmpxchg.h>
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/*
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* Atomic operations that C can't guarantee us. Useful for
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* resource counting etc...
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*
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* But use these as seldom as possible since they are much slower
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* than regular operations.
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*/
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/*
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* To ensure dependency ordering is preserved for the _relaxed and
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* _release atomics, an smp_read_barrier_depends() is unconditionally
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* inserted into the _relaxed variants, which are used to build the
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* barriered versions. Avoid redundant back-to-back fences in the
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* _acquire and _fence versions.
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*/
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#define __atomic_acquire_fence()
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#define __atomic_post_full_fence()
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#define ATOMIC_INIT(i) { (i) }
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#define ATOMIC64_INIT(i) { (i) }
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#define atomic_read(v) READ_ONCE((v)->counter)
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#define atomic64_read(v) READ_ONCE((v)->counter)
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#define atomic_set(v,i) WRITE_ONCE((v)->counter, (i))
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#define atomic64_set(v,i) WRITE_ONCE((v)->counter, (i))
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/*
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* To get proper branch prediction for the main line, we must branch
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* forward to code at the end of this object's .text section, then
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* branch back to restart the operation.
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*/
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#define ATOMIC_OP(op, asm_op) \
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static __inline__ void atomic_##op(int i, atomic_t * v) \
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{ \
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unsigned long temp; \
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__asm__ __volatile__( \
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"1: ldl_l %0,%1\n" \
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" " #asm_op " %0,%2,%0\n" \
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" stl_c %0,%1\n" \
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" beq %0,2f\n" \
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".subsection 2\n" \
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"2: br 1b\n" \
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".previous" \
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:"=&r" (temp), "=m" (v->counter) \
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:"Ir" (i), "m" (v->counter)); \
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} \
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#define ATOMIC_OP_RETURN(op, asm_op) \
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static inline int atomic_##op##_return_relaxed(int i, atomic_t *v) \
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{ \
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long temp, result; \
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__asm__ __volatile__( \
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"1: ldl_l %0,%1\n" \
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" " #asm_op " %0,%3,%2\n" \
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" " #asm_op " %0,%3,%0\n" \
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" stl_c %0,%1\n" \
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" beq %0,2f\n" \
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".subsection 2\n" \
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"2: br 1b\n" \
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".previous" \
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:"=&r" (temp), "=m" (v->counter), "=&r" (result) \
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:"Ir" (i), "m" (v->counter) : "memory"); \
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smp_read_barrier_depends(); \
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return result; \
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}
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#define ATOMIC_FETCH_OP(op, asm_op) \
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static inline int atomic_fetch_##op##_relaxed(int i, atomic_t *v) \
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{ \
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long temp, result; \
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__asm__ __volatile__( \
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"1: ldl_l %2,%1\n" \
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" " #asm_op " %2,%3,%0\n" \
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" stl_c %0,%1\n" \
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" beq %0,2f\n" \
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".subsection 2\n" \
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"2: br 1b\n" \
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".previous" \
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:"=&r" (temp), "=m" (v->counter), "=&r" (result) \
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:"Ir" (i), "m" (v->counter) : "memory"); \
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smp_read_barrier_depends(); \
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return result; \
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}
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#define ATOMIC64_OP(op, asm_op) \
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static __inline__ void atomic64_##op(s64 i, atomic64_t * v) \
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{ \
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s64 temp; \
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__asm__ __volatile__( \
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"1: ldq_l %0,%1\n" \
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" " #asm_op " %0,%2,%0\n" \
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" stq_c %0,%1\n" \
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" beq %0,2f\n" \
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".subsection 2\n" \
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"2: br 1b\n" \
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".previous" \
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:"=&r" (temp), "=m" (v->counter) \
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:"Ir" (i), "m" (v->counter)); \
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} \
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#define ATOMIC64_OP_RETURN(op, asm_op) \
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static __inline__ s64 atomic64_##op##_return_relaxed(s64 i, atomic64_t * v) \
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{ \
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s64 temp, result; \
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__asm__ __volatile__( \
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"1: ldq_l %0,%1\n" \
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" " #asm_op " %0,%3,%2\n" \
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" " #asm_op " %0,%3,%0\n" \
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" stq_c %0,%1\n" \
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" beq %0,2f\n" \
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".subsection 2\n" \
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"2: br 1b\n" \
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".previous" \
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:"=&r" (temp), "=m" (v->counter), "=&r" (result) \
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:"Ir" (i), "m" (v->counter) : "memory"); \
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smp_read_barrier_depends(); \
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return result; \
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}
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#define ATOMIC64_FETCH_OP(op, asm_op) \
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static __inline__ s64 atomic64_fetch_##op##_relaxed(s64 i, atomic64_t * v) \
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{ \
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s64 temp, result; \
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__asm__ __volatile__( \
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"1: ldq_l %2,%1\n" \
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" " #asm_op " %2,%3,%0\n" \
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" stq_c %0,%1\n" \
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" beq %0,2f\n" \
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".subsection 2\n" \
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"2: br 1b\n" \
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".previous" \
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:"=&r" (temp), "=m" (v->counter), "=&r" (result) \
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:"Ir" (i), "m" (v->counter) : "memory"); \
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smp_read_barrier_depends(); \
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return result; \
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}
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#define ATOMIC_OPS(op) \
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ATOMIC_OP(op, op##l) \
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ATOMIC_OP_RETURN(op, op##l) \
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ATOMIC_FETCH_OP(op, op##l) \
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ATOMIC64_OP(op, op##q) \
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ATOMIC64_OP_RETURN(op, op##q) \
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ATOMIC64_FETCH_OP(op, op##q)
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ATOMIC_OPS(add)
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ATOMIC_OPS(sub)
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#define atomic_add_return_relaxed atomic_add_return_relaxed
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#define atomic_sub_return_relaxed atomic_sub_return_relaxed
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#define atomic_fetch_add_relaxed atomic_fetch_add_relaxed
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#define atomic_fetch_sub_relaxed atomic_fetch_sub_relaxed
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#define atomic64_add_return_relaxed atomic64_add_return_relaxed
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#define atomic64_sub_return_relaxed atomic64_sub_return_relaxed
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#define atomic64_fetch_add_relaxed atomic64_fetch_add_relaxed
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#define atomic64_fetch_sub_relaxed atomic64_fetch_sub_relaxed
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#define atomic_andnot atomic_andnot
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#define atomic64_andnot atomic64_andnot
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(op, asm) \
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ATOMIC_OP(op, asm) \
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ATOMIC_FETCH_OP(op, asm) \
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ATOMIC64_OP(op, asm) \
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ATOMIC64_FETCH_OP(op, asm)
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ATOMIC_OPS(and, and)
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ATOMIC_OPS(andnot, bic)
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ATOMIC_OPS(or, bis)
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ATOMIC_OPS(xor, xor)
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#define atomic_fetch_and_relaxed atomic_fetch_and_relaxed
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#define atomic_fetch_andnot_relaxed atomic_fetch_andnot_relaxed
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#define atomic_fetch_or_relaxed atomic_fetch_or_relaxed
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#define atomic_fetch_xor_relaxed atomic_fetch_xor_relaxed
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#define atomic64_fetch_and_relaxed atomic64_fetch_and_relaxed
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#define atomic64_fetch_andnot_relaxed atomic64_fetch_andnot_relaxed
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#define atomic64_fetch_or_relaxed atomic64_fetch_or_relaxed
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#define atomic64_fetch_xor_relaxed atomic64_fetch_xor_relaxed
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#undef ATOMIC_OPS
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#undef ATOMIC64_FETCH_OP
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#undef ATOMIC64_OP_RETURN
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#undef ATOMIC64_OP
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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#define atomic64_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
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#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
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#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
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#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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/**
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* atomic_fetch_add_unless - add unless the number is a given value
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* @v: pointer of type atomic_t
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* @a: the amount to add to v...
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* @u: ...unless v is equal to u.
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*
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* Atomically adds @a to @v, so long as it was not @u.
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* Returns the old value of @v.
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*/
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static __inline__ int atomic_fetch_add_unless(atomic_t *v, int a, int u)
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{
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int c, new, old;
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smp_mb();
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__asm__ __volatile__(
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"1: ldl_l %[old],%[mem]\n"
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" cmpeq %[old],%[u],%[c]\n"
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" addl %[old],%[a],%[new]\n"
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" bne %[c],2f\n"
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" stl_c %[new],%[mem]\n"
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" beq %[new],3f\n"
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"2:\n"
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".subsection 2\n"
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"3: br 1b\n"
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".previous"
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: [old] "=&r"(old), [new] "=&r"(new), [c] "=&r"(c)
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: [mem] "m"(*v), [a] "rI"(a), [u] "rI"((long)u)
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: "memory");
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smp_mb();
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return old;
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}
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#define atomic_fetch_add_unless atomic_fetch_add_unless
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/**
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* atomic64_fetch_add_unless - add unless the number is a given value
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* @v: pointer of type atomic64_t
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* @a: the amount to add to v...
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* @u: ...unless v is equal to u.
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*
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* Atomically adds @a to @v, so long as it was not @u.
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* Returns the old value of @v.
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*/
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static __inline__ s64 atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u)
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{
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s64 c, new, old;
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smp_mb();
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__asm__ __volatile__(
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"1: ldq_l %[old],%[mem]\n"
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" cmpeq %[old],%[u],%[c]\n"
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" addq %[old],%[a],%[new]\n"
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" bne %[c],2f\n"
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" stq_c %[new],%[mem]\n"
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" beq %[new],3f\n"
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"2:\n"
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".subsection 2\n"
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"3: br 1b\n"
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".previous"
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: [old] "=&r"(old), [new] "=&r"(new), [c] "=&r"(c)
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: [mem] "m"(*v), [a] "rI"(a), [u] "rI"(u)
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: "memory");
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smp_mb();
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return old;
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}
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#define atomic64_fetch_add_unless atomic64_fetch_add_unless
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/*
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* atomic64_dec_if_positive - decrement by 1 if old value positive
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* @v: pointer of type atomic_t
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*
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* The function returns the old value of *v minus 1, even if
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* the atomic variable, v, was not decremented.
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*/
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static inline s64 atomic64_dec_if_positive(atomic64_t *v)
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{
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s64 old, tmp;
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smp_mb();
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__asm__ __volatile__(
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"1: ldq_l %[old],%[mem]\n"
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" subq %[old],1,%[tmp]\n"
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" ble %[old],2f\n"
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" stq_c %[tmp],%[mem]\n"
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" beq %[tmp],3f\n"
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"2:\n"
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".subsection 2\n"
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"3: br 1b\n"
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".previous"
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: [old] "=&r"(old), [tmp] "=&r"(tmp)
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: [mem] "m"(*v)
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: "memory");
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smp_mb();
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return old - 1;
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}
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#define atomic64_dec_if_positive atomic64_dec_if_positive
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#endif /* _ALPHA_ATOMIC_H */
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