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a1f487d75c
Various bits of iop32x are now in their traditional locations in plat-iop, mach-iop/include/mach/ and in include/asm/mach/hardware. As nothing outside of the iop32x mach code references these any more, this can all be moved into one place now. The only remaining things in the include/mach/ directory are now the NR_IRQS definition, the entry-macros.S file and the the decompressor uart access. After the irqchip code has been converted to SPARSE_IRQ and GENERIC_IRQ_MULTI_HANDLER, it can be moved to ARCH_MULTIPLATFORM. Link: https://lore.kernel.org/r/20190809163334.489360-7-arnd@arndb.de Signed-off-by: Arnd Bergmann <arnd@arndb.de>
32 lines
917 B
ArmAsm
32 lines
917 B
ArmAsm
/*
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* arch/arm/mach-iop32x/include/mach/entry-macro.S
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*
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* Low-level IRQ helper macros for IOP32x-based platforms
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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.macro get_irqnr_preamble, base, tmp
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mrc p15, 0, \tmp, c15, c1, 0
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orr \tmp, \tmp, #(1 << 6)
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mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
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mrc p15, 0, \tmp, c15, c1, 0
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mov \tmp, \tmp
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sub pc, pc, #4 @ cp_wait
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC
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cmp \irqstat, #0
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clzne \irqnr, \irqstat
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rsbne \irqnr, \irqnr, #31
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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mrc p15, 0, \tmp1, c15, c1, 0
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ands \tmp2, \tmp1, #(1 << 6)
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bicne \tmp1, \tmp1, #(1 << 6)
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mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
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.endm
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