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e9670ccb39
Enable low-level debugging support for RZ/A2M (r7s9210). The RZA2MEVB board uses either SCIF2 (SDRAM enabled) or SCIF4 (HyperRAM only) for the serial console. Note that "SCIFA" serial ports on RZ/A2 SoCs use a compressed register layout, hence add support for that to renesas-scif.S. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
54 lines
1.0 KiB
ArmAsm
54 lines
1.0 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Renesas SCIF(A) debugging macro include header
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*
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* Based on r8a7790.S
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*
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* Copyright (C) 2012-2013 Renesas Electronics Corporation
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* Copyright (C) 1994-1999 Russell King
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*/
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#define SCIF_PHYS CONFIG_DEBUG_UART_PHYS
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#define SCIF_VIRT ((SCIF_PHYS & 0x00ffffff) | 0xfd000000)
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#if defined(CONFIG_DEBUG_R7S9210_SCIF2) || defined(CONFIG_DEBUG_R7S9210_SCIF4)
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/* RZ/A2 SCIFA */
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#define FTDR 0x06
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#define FSR 0x08
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#elif CONFIG_DEBUG_UART_PHYS < 0xe6e00000
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/* SCIFA */
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#define FTDR 0x20
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#define FSR 0x14
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#else
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/* SCIF */
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#define FTDR 0x0c
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#define FSR 0x10
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#endif
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#define TDFE (1 << 5)
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#define TEND (1 << 6)
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.macro addruart, rp, rv, tmp
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ldr \rp, =SCIF_PHYS
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ldr \rv, =SCIF_VIRT
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.endm
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.macro waituart, rd, rx
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1001: ldrh \rd, [\rx, #FSR]
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tst \rd, #TDFE
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beq 1001b
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.endm
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.macro senduart, rd, rx
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strb \rd, [\rx, #FTDR]
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ldrh \rd, [\rx, #FSR]
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bic \rd, \rd, #TEND
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strh \rd, [\rx, #FSR]
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.endm
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.macro busyuart, rd, rx
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1001: ldrh \rd, [\rx, #FSR]
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tst \rd, #TEND
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beq 1001b
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.endm
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