386 lines
9.2 KiB
C
386 lines
9.2 KiB
C
/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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/*
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* Pre-requisites: headers required by header of this unit
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*/
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#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
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#include "hw_translate_dcn21.h"
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#include "dm_services.h"
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#include "include/gpio_types.h"
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#include "../hw_translate.h"
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#include "dcn/dcn_2_1_0_offset.h"
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#include "dcn/dcn_2_1_0_sh_mask.h"
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#include "renoir_ip_offset.h"
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/* begin *********************
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* macros to expend register list macro defined in HW object header file */
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/* DCN */
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#define block HPD
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#define reg_num 0
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#undef BASE_INNER
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#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
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#define BASE(seg) BASE_INNER(seg)
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#undef REG
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#define REG(reg_name)\
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BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
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#define SF_HPD(reg_name, field_name, post_fix)\
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.field_name = reg_name ## __ ## field_name ## post_fix
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/* macros to expend register list macro defined in HW object header file
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* end *********************/
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static bool offset_to_id(
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uint32_t offset,
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uint32_t mask,
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enum gpio_id *id,
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uint32_t *en)
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{
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switch (offset) {
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/* GENERIC */
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case REG(DC_GPIO_GENERIC_A):
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*id = GPIO_ID_GENERIC;
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switch (mask) {
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case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
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*en = GPIO_GENERIC_A;
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return true;
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case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
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*en = GPIO_GENERIC_B;
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return true;
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case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
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*en = GPIO_GENERIC_C;
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return true;
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case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
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*en = GPIO_GENERIC_D;
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return true;
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case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
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*en = GPIO_GENERIC_E;
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return true;
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case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
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*en = GPIO_GENERIC_F;
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return true;
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case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK:
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*en = GPIO_GENERIC_G;
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return true;
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default:
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ASSERT_CRITICAL(false);
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#ifdef PALLADIUM_SUPPORTED
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*en = GPIO_DDC_LINE_DDC1;
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return true;
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#endif
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return false;
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}
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break;
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/* HPD */
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case REG(DC_GPIO_HPD_A):
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*id = GPIO_ID_HPD;
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switch (mask) {
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case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
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*en = GPIO_HPD_1;
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return true;
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case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
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*en = GPIO_HPD_2;
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return true;
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case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
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*en = GPIO_HPD_3;
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return true;
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case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
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*en = GPIO_HPD_4;
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return true;
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case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
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*en = GPIO_HPD_5;
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return true;
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case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK:
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*en = GPIO_HPD_6;
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return true;
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default:
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ASSERT_CRITICAL(false);
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return false;
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}
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break;
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/* REG(DC_GPIO_GENLK_MASK */
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case REG(DC_GPIO_GENLK_A):
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*id = GPIO_ID_GSL;
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switch (mask) {
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case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
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*en = GPIO_GSL_GENLOCK_CLOCK;
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return true;
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case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
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*en = GPIO_GSL_GENLOCK_VSYNC;
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return true;
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case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
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*en = GPIO_GSL_SWAPLOCK_A;
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return true;
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case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
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*en = GPIO_GSL_SWAPLOCK_B;
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return true;
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default:
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ASSERT_CRITICAL(false);
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return false;
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}
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break;
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/* DDC */
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/* we don't care about the GPIO_ID for DDC
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* in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
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* directly in the create method */
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case REG(DC_GPIO_DDC1_A):
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*en = GPIO_DDC_LINE_DDC1;
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return true;
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case REG(DC_GPIO_DDC2_A):
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*en = GPIO_DDC_LINE_DDC2;
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return true;
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case REG(DC_GPIO_DDC3_A):
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*en = GPIO_DDC_LINE_DDC3;
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return true;
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case REG(DC_GPIO_DDC4_A):
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*en = GPIO_DDC_LINE_DDC4;
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return true;
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case REG(DC_GPIO_DDC5_A):
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*en = GPIO_DDC_LINE_DDC5;
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return true;
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case REG(DC_GPIO_DDCVGA_A):
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*en = GPIO_DDC_LINE_DDC_VGA;
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return true;
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// case REG(DC_GPIO_I2CPAD_A): not exit
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// case REG(DC_GPIO_PWRSEQ_A):
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// case REG(DC_GPIO_PAD_STRENGTH_1):
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// case REG(DC_GPIO_PAD_STRENGTH_2):
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// case REG(DC_GPIO_DEBUG):
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/* UNEXPECTED */
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default:
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// case REG(DC_GPIO_SYNCA_A): not exist
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#ifdef PALLADIUM_SUPPORTED
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*id = GPIO_ID_HPD;
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*en = GPIO_DDC_LINE_DDC1;
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return true;
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#endif
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ASSERT_CRITICAL(false);
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return false;
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}
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}
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static bool id_to_offset(
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enum gpio_id id,
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uint32_t en,
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struct gpio_pin_info *info)
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{
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bool result = true;
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switch (id) {
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case GPIO_ID_DDC_DATA:
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info->mask = DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK;
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switch (en) {
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case GPIO_DDC_LINE_DDC1:
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info->offset = REG(DC_GPIO_DDC1_A);
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break;
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case GPIO_DDC_LINE_DDC2:
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info->offset = REG(DC_GPIO_DDC2_A);
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break;
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case GPIO_DDC_LINE_DDC3:
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info->offset = REG(DC_GPIO_DDC3_A);
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break;
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case GPIO_DDC_LINE_DDC4:
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info->offset = REG(DC_GPIO_DDC4_A);
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break;
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case GPIO_DDC_LINE_DDC5:
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info->offset = REG(DC_GPIO_DDC5_A);
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break;
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case GPIO_DDC_LINE_DDC_VGA:
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info->offset = REG(DC_GPIO_DDCVGA_A);
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break;
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case GPIO_DDC_LINE_I2C_PAD:
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default:
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ASSERT_CRITICAL(false);
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result = false;
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}
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break;
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case GPIO_ID_DDC_CLOCK:
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info->mask = DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK;
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switch (en) {
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case GPIO_DDC_LINE_DDC1:
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info->offset = REG(DC_GPIO_DDC1_A);
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break;
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case GPIO_DDC_LINE_DDC2:
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info->offset = REG(DC_GPIO_DDC2_A);
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break;
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case GPIO_DDC_LINE_DDC3:
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info->offset = REG(DC_GPIO_DDC3_A);
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break;
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case GPIO_DDC_LINE_DDC4:
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info->offset = REG(DC_GPIO_DDC4_A);
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break;
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case GPIO_DDC_LINE_DDC5:
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info->offset = REG(DC_GPIO_DDC5_A);
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break;
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case GPIO_DDC_LINE_DDC_VGA:
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info->offset = REG(DC_GPIO_DDCVGA_A);
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break;
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case GPIO_DDC_LINE_I2C_PAD:
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default:
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ASSERT_CRITICAL(false);
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result = false;
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}
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break;
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case GPIO_ID_GENERIC:
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info->offset = REG(DC_GPIO_GENERIC_A);
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switch (en) {
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case GPIO_GENERIC_A:
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info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
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break;
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case GPIO_GENERIC_B:
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info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
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break;
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case GPIO_GENERIC_C:
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info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
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break;
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case GPIO_GENERIC_D:
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info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
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break;
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case GPIO_GENERIC_E:
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info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
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break;
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case GPIO_GENERIC_F:
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info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
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break;
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case GPIO_GENERIC_G:
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info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;
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break;
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default:
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ASSERT_CRITICAL(false);
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result = false;
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}
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break;
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case GPIO_ID_HPD:
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info->offset = REG(DC_GPIO_HPD_A);
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switch (en) {
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case GPIO_HPD_1:
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info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
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break;
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case GPIO_HPD_2:
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info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
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break;
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case GPIO_HPD_3:
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info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
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break;
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case GPIO_HPD_4:
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info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
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break;
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case GPIO_HPD_5:
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info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
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break;
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case GPIO_HPD_6:
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info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;
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break;
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default:
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ASSERT_CRITICAL(false);
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#ifdef PALLADIUM_SUPPORTED
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info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
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result = true;
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#endif
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result = false;
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}
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break;
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case GPIO_ID_GSL:
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switch (en) {
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case GPIO_GSL_GENLOCK_CLOCK:
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/*not implmented*/
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ASSERT_CRITICAL(false);
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result = false;
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break;
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case GPIO_GSL_GENLOCK_VSYNC:
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/*not implmented*/
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ASSERT_CRITICAL(false);
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result = false;
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break;
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case GPIO_GSL_SWAPLOCK_A:
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/*not implmented*/
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ASSERT_CRITICAL(false);
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result = false;
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break;
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case GPIO_GSL_SWAPLOCK_B:
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/*not implmented*/
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ASSERT_CRITICAL(false);
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result = false;
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break;
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default:
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ASSERT_CRITICAL(false);
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result = false;
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}
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break;
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case GPIO_ID_SYNC:
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case GPIO_ID_VIP_PAD:
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default:
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ASSERT_CRITICAL(false);
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result = false;
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}
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if (result) {
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info->offset_y = info->offset + 2;
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info->offset_en = info->offset + 1;
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info->offset_mask = info->offset - 1;
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info->mask_y = info->mask;
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info->mask_en = info->mask;
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info->mask_mask = info->mask;
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}
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return result;
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}
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/* function table */
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static const struct hw_translate_funcs funcs = {
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.offset_to_id = offset_to_id,
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.id_to_offset = id_to_offset,
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};
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/*
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* dal_hw_translate_dcn10_init
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*
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* @brief
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* Initialize Hw translate function pointers.
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*
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* @param
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* struct hw_translate *tr - [out] struct of function pointers
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*
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*/
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void dal_hw_translate_dcn21_init(struct hw_translate *tr)
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{
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tr->funcs = &funcs;
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}
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#endif
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