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1d113893ff
[ Upstream commit f6f1f8e6e3eea25f539105d48166e91f0ab46dd1 ] A dummy zero bit is sent preceding the data during a read transfer by the Microchip 93LC46B eeprom (section 2.7 of[1]). This results in right shift of data during a read. In order to ignore this bit a quirk can be added to send an extra zero bit after the read address. Add a quirk to ignore the zero bit sent before data by adding a zero bit after the read address. [1] - https://www.mouser.com/datasheet/2/268/20001749K-277859.pdf Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20210105105817.17644-3-a-govindraju@ti.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
30 lines
879 B
C
30 lines
879 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Module: eeprom_93xx46
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* platform description for 93xx46 EEPROMs.
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*/
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#include <linux/gpio/consumer.h>
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struct eeprom_93xx46_platform_data {
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unsigned char flags;
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#define EE_ADDR8 0x01 /* 8 bit addr. cfg */
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#define EE_ADDR16 0x02 /* 16 bit addr. cfg */
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#define EE_READONLY 0x08 /* forbid writing */
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unsigned int quirks;
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/* Single word read transfers only; no sequential read. */
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#define EEPROM_93XX46_QUIRK_SINGLE_WORD_READ (1 << 0)
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/* Instructions such as EWEN are (addrlen + 2) in length. */
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#define EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH (1 << 1)
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/* Add extra cycle after address during a read */
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#define EEPROM_93XX46_QUIRK_EXTRA_READ_CYCLE BIT(2)
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/*
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* optional hooks to control additional logic
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* before and after spi transfer.
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*/
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void (*prepare)(void *);
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void (*finish)(void *);
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struct gpio_desc *select;
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};
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