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The clock output is generally only used for testing and development and not used to daisy-chain PHYs. It's just a source of RF noise afterward. Add a mux value for "off". I've added it as another enumeration to the output property. In the actual PHY, the mux and the output enable are independently controllable. However, it doesn't seem useful to be able to describe the mux setting when the output is disabled. Document that PHY's default setting will be left as is if the property is omitted. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
59 lines
2.6 KiB
Plaintext
59 lines
2.6 KiB
Plaintext
* Texas Instruments - dp83867 Giga bit ethernet phy
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Required properties:
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- reg - The ID number for the phy, usually a small integer
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- ti,rx-internal-delay - RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
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for applicable values. Required only if interface type is
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PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID
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- ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
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for applicable values. Required only if interface type is
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PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID
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- ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
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for applicable values
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Note: If the interface type is PHY_INTERFACE_MODE_RGMII the TX/RX clock delays
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will be left at their default values, as set by the PHY's pin strapping.
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The default strapping will use a delay of 2.00 ns. Thus
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PHY_INTERFACE_MODE_RGMII, by default, does not behave as RGMII with no
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internal delay, but as PHY_INTERFACE_MODE_RGMII_ID. The device tree
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should use "rgmii-id" if internal delays are desired as this may be
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changed in future to cause "rgmii" mode to disable delays.
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Optional property:
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- ti,min-output-impedance - MAC Interface Impedance control to set
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the programmable output impedance to
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minimum value (35 ohms).
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- ti,max-output-impedance - MAC Interface Impedance control to set
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the programmable output impedance to
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maximum value (70 ohms).
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- ti,dp83867-rxctrl-strap-quirk - This denotes the fact that the
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board has RX_DV/RX_CTRL pin strapped in
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mode 1 or 2. To ensure PHY operation,
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there are specific actions that
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software needs to take when this pin is
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strapped in these modes. See data manual
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for details.
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- ti,clk-output-sel - Muxing option for CLK_OUT pin. See dt-bindings/net/ti-dp83867.h
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for applicable values. The CLK_OUT pin can also
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be disabled by this property. When omitted, the
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PHY's default will be left as is.
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Note: ti,min-output-impedance and ti,max-output-impedance are mutually
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exclusive. When both properties are present ti,max-output-impedance
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takes precedence.
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Default child nodes are standard Ethernet PHY device
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nodes as described in Documentation/devicetree/bindings/net/phy.txt
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Example:
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ethernet-phy@0 {
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reg = <0>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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};
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Datasheet can be found:
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http://www.ti.com/product/DP83867IR/datasheet
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