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https://github.com/brain-hackers/linux-brain.git
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fca93d34f3
[ Upstream commit360fe725f8] After commite509bd7da1("genirq: Allow migration of chained interrupts by installing default action") Loongson-3 fails at here: setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction); This is because both chained_action and cascade_irqaction don't have IRQF_SHARED flag. This will cause Loongson-3 resume fails because HPET timer interrupt can't be delivered during S3. So we set the irqchip of the chained irq to loongson_irq_chip which doesn't disable the chained irq in CP0.Status. Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20434/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhuacai@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
102 lines
2.4 KiB
C
102 lines
2.4 KiB
C
#include <loongson.h>
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#include <irq.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <asm/irq_cpu.h>
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#include <asm/i8259.h>
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#include <asm/mipsregs.h>
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#include "smp.h"
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unsigned int ht_irq[] = {0, 1, 3, 4, 5, 6, 7, 8, 12, 14, 15};
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static void ht_irqdispatch(void)
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{
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unsigned int i, irq;
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irq = LOONGSON_HT1_INT_VECTOR(0);
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LOONGSON_HT1_INT_VECTOR(0) = irq; /* Acknowledge the IRQs */
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for (i = 0; i < ARRAY_SIZE(ht_irq); i++) {
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if (irq & (0x1 << ht_irq[i]))
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do_IRQ(ht_irq[i]);
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}
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}
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#define UNUSED_IPS (CAUSEF_IP5 | CAUSEF_IP4 | CAUSEF_IP1 | CAUSEF_IP0)
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void mach_irq_dispatch(unsigned int pending)
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{
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if (pending & CAUSEF_IP7)
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do_IRQ(LOONGSON_TIMER_IRQ);
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#if defined(CONFIG_SMP)
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if (pending & CAUSEF_IP6)
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loongson3_ipi_interrupt(NULL);
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#endif
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if (pending & CAUSEF_IP3)
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ht_irqdispatch();
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if (pending & CAUSEF_IP2)
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do_IRQ(LOONGSON_UART_IRQ);
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if (pending & UNUSED_IPS) {
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pr_err("%s : spurious interrupt\n", __func__);
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spurious_interrupt();
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}
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}
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static inline void mask_loongson_irq(struct irq_data *d) { }
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static inline void unmask_loongson_irq(struct irq_data *d) { }
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/* For MIPS IRQs which shared by all cores */
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static struct irq_chip loongson_irq_chip = {
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.name = "Loongson",
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.irq_ack = mask_loongson_irq,
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.irq_mask = mask_loongson_irq,
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.irq_mask_ack = mask_loongson_irq,
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.irq_unmask = unmask_loongson_irq,
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.irq_eoi = unmask_loongson_irq,
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};
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void irq_router_init(void)
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{
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int i;
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/* route LPC int to cpu core0 int 0 */
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LOONGSON_INT_ROUTER_LPC =
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LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 0);
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/* route HT1 int0 ~ int7 to cpu core0 INT1*/
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for (i = 0; i < 8; i++)
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LOONGSON_INT_ROUTER_HT1(i) =
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LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 1);
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/* enable HT1 interrupt */
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LOONGSON_HT1_INTN_EN(0) = 0xffffffff;
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/* enable router interrupt intenset */
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LOONGSON_INT_ROUTER_INTENSET =
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LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10;
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}
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void __init mach_init_irq(void)
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{
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clear_c0_status(ST0_IM | ST0_BEV);
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irq_router_init();
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mips_cpu_irq_init();
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init_i8259_irqs();
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irq_set_chip_and_handler(LOONGSON_UART_IRQ,
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&loongson_irq_chip, handle_percpu_irq);
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irq_set_chip_and_handler(LOONGSON_BRIDGE_IRQ,
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&loongson_irq_chip, handle_percpu_irq);
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set_c0_status(STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP6);
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}
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#ifdef CONFIG_HOTPLUG_CPU
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void fixup_irqs(void)
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{
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irq_cpu_offline();
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clear_c0_status(ST0_IM);
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}
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#endif
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