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https://github.com/brain-hackers/linux-brain.git
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3c751807c9
[ Upstream commit 5c41aaad40 ]
Building drivers/mtd/nand/raw/nandsim.c on arch/hexagon/ produces a
printk format build warning. This is due to hexagon's ffs() being
coded as returning long instead of int.
Fix the printk format warning by changing all of hexagon's ffs() and
fls() functions to return int instead of long. The variables that
they return are already int instead of long. This return type
matches the return type in <asm-generic/bitops/>.
../drivers/mtd/nand/raw/nandsim.c: In function 'init_nandsim':
../drivers/mtd/nand/raw/nandsim.c:760:2: warning: format '%u' expects argument of type 'unsigned int', but argument 2 has type 'long int' [-Wformat]
There are no ffs() or fls() allmodconfig build errors after making this
change.
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Richard Kuo <rkuo@codeaurora.org>
Cc: linux-hexagon@vger.kernel.org
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Patch-mainline: linux-kernel @ 07/22/2018, 16:03
Signed-off-by: Richard Kuo <rkuo@codeaurora.org>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
299 lines
6.6 KiB
C
299 lines
6.6 KiB
C
/*
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* Bit operations for the Hexagon architecture
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*
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* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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#ifndef _ASM_BITOPS_H
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#define _ASM_BITOPS_H
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#include <linux/compiler.h>
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#include <asm/byteorder.h>
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#include <asm/atomic.h>
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#include <asm/barrier.h>
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#ifdef __KERNEL__
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/*
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* The offset calculations for these are based on BITS_PER_LONG == 32
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* (i.e. I get to shift by #5-2 (32 bits per long, 4 bytes per access),
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* mask by 0x0000001F)
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*
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* Typically, R10 is clobbered for address, R11 bit nr, and R12 is temp
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*/
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/**
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* test_and_clear_bit - clear a bit and return its old value
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* @nr: bit number to clear
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* @addr: pointer to memory
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*/
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static inline int test_and_clear_bit(int nr, volatile void *addr)
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{
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int oldval;
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__asm__ __volatile__ (
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" {R10 = %1; R11 = asr(%2,#5); }\n"
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" {R10 += asl(R11,#2); R11 = and(%2,#0x1f)}\n"
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"1: R12 = memw_locked(R10);\n"
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" { P0 = tstbit(R12,R11); R12 = clrbit(R12,R11); }\n"
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" memw_locked(R10,P1) = R12;\n"
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" {if !P1 jump 1b; %0 = mux(P0,#1,#0);}\n"
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: "=&r" (oldval)
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: "r" (addr), "r" (nr)
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: "r10", "r11", "r12", "p0", "p1", "memory"
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);
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return oldval;
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}
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/**
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* test_and_set_bit - set a bit and return its old value
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* @nr: bit number to set
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* @addr: pointer to memory
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*/
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static inline int test_and_set_bit(int nr, volatile void *addr)
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{
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int oldval;
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__asm__ __volatile__ (
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" {R10 = %1; R11 = asr(%2,#5); }\n"
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" {R10 += asl(R11,#2); R11 = and(%2,#0x1f)}\n"
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"1: R12 = memw_locked(R10);\n"
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" { P0 = tstbit(R12,R11); R12 = setbit(R12,R11); }\n"
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" memw_locked(R10,P1) = R12;\n"
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" {if !P1 jump 1b; %0 = mux(P0,#1,#0);}\n"
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: "=&r" (oldval)
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: "r" (addr), "r" (nr)
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: "r10", "r11", "r12", "p0", "p1", "memory"
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);
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return oldval;
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}
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/**
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* test_and_change_bit - toggle a bit and return its old value
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* @nr: bit number to set
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* @addr: pointer to memory
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*/
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static inline int test_and_change_bit(int nr, volatile void *addr)
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{
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int oldval;
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__asm__ __volatile__ (
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" {R10 = %1; R11 = asr(%2,#5); }\n"
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" {R10 += asl(R11,#2); R11 = and(%2,#0x1f)}\n"
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"1: R12 = memw_locked(R10);\n"
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" { P0 = tstbit(R12,R11); R12 = togglebit(R12,R11); }\n"
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" memw_locked(R10,P1) = R12;\n"
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" {if !P1 jump 1b; %0 = mux(P0,#1,#0);}\n"
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: "=&r" (oldval)
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: "r" (addr), "r" (nr)
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: "r10", "r11", "r12", "p0", "p1", "memory"
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);
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return oldval;
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}
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/*
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* Atomic, but doesn't care about the return value.
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* Rewrite later to save a cycle or two.
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*/
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static inline void clear_bit(int nr, volatile void *addr)
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{
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test_and_clear_bit(nr, addr);
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}
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static inline void set_bit(int nr, volatile void *addr)
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{
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test_and_set_bit(nr, addr);
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}
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static inline void change_bit(int nr, volatile void *addr)
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{
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test_and_change_bit(nr, addr);
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}
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/*
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* These are allowed to be non-atomic. In fact the generic flavors are
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* in non-atomic.h. Would it be better to use intrinsics for this?
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*
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* OK, writes in our architecture do not invalidate LL/SC, so this has to
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* be atomic, particularly for things like slab_lock and slab_unlock.
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*
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*/
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static inline void __clear_bit(int nr, volatile unsigned long *addr)
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{
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test_and_clear_bit(nr, addr);
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}
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static inline void __set_bit(int nr, volatile unsigned long *addr)
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{
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test_and_set_bit(nr, addr);
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}
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static inline void __change_bit(int nr, volatile unsigned long *addr)
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{
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test_and_change_bit(nr, addr);
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}
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/* Apparently, at least some of these are allowed to be non-atomic */
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static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
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{
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return test_and_clear_bit(nr, addr);
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}
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static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
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{
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return test_and_set_bit(nr, addr);
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}
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static inline int __test_and_change_bit(int nr, volatile unsigned long *addr)
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{
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return test_and_change_bit(nr, addr);
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}
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static inline int __test_bit(int nr, const volatile unsigned long *addr)
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{
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int retval;
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asm volatile(
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"{P0 = tstbit(%1,%2); if (P0.new) %0 = #1; if (!P0.new) %0 = #0;}\n"
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: "=&r" (retval)
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: "r" (addr[BIT_WORD(nr)]), "r" (nr % BITS_PER_LONG)
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: "p0"
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);
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return retval;
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}
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#define test_bit(nr, addr) __test_bit(nr, addr)
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/*
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* ffz - find first zero in word.
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* @word: The word to search
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*
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* Undefined if no zero exists, so code should check against ~0UL first.
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*/
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static inline long ffz(int x)
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{
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int r;
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asm("%0 = ct1(%1);\n"
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: "=&r" (r)
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: "r" (x));
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return r;
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}
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/*
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* fls - find last (most-significant) bit set
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* @x: the word to search
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*
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* This is defined the same way as ffs.
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* Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
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*/
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static inline int fls(int x)
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{
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int r;
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asm("{ %0 = cl0(%1);}\n"
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"%0 = sub(#32,%0);\n"
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: "=&r" (r)
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: "r" (x)
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: "p0");
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return r;
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}
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/*
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* ffs - find first bit set
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* @x: the word to search
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*
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* This is defined the same way as
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* the libc and compiler builtin ffs routines, therefore
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* differs in spirit from the above ffz (man ffs).
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*/
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static inline int ffs(int x)
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{
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int r;
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asm("{ P0 = cmp.eq(%1,#0); %0 = ct0(%1);}\n"
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"{ if P0 %0 = #0; if !P0 %0 = add(%0,#1);}\n"
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: "=&r" (r)
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: "r" (x)
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: "p0");
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return r;
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}
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/*
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* __ffs - find first bit in word.
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* @word: The word to search
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*
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* Undefined if no bit exists, so code should check against 0 first.
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*
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* bits_per_long assumed to be 32
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* numbering starts at 0 I think (instead of 1 like ffs)
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*/
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static inline unsigned long __ffs(unsigned long word)
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{
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int num;
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asm("%0 = ct0(%1);\n"
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: "=&r" (num)
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: "r" (word));
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return num;
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}
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/*
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* __fls - find last (most-significant) set bit in a long word
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* @word: the word to search
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*
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* Undefined if no set bit exists, so code should check against 0 first.
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* bits_per_long assumed to be 32
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*/
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static inline unsigned long __fls(unsigned long word)
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{
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int num;
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asm("%0 = cl0(%1);\n"
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"%0 = sub(#31,%0);\n"
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: "=&r" (num)
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: "r" (word));
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return num;
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}
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#include <asm-generic/bitops/lock.h>
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#include <asm-generic/bitops/find.h>
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#include <asm-generic/bitops/fls64.h>
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#include <asm-generic/bitops/sched.h>
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#include <asm-generic/bitops/hweight.h>
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#include <asm-generic/bitops/le.h>
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#include <asm-generic/bitops/ext2-atomic.h>
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#endif /* __KERNEL__ */
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#endif
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