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20d330645c
On some MIPS systems, a subset of devices may have DMA coherent with CPU caches. For example in systems including a MIPS I/O Coherence Unit (IOCU), some devices may be connected to that IOCU whilst others are not. Prior to this patch, we have a plat_device_is_coherent() function but no implementation which does anything besides return a global true or false, optionally chosen at runtime. For devices such as those described above this is insufficient. Fix this by tracking DMA coherence on a per-device basis with a dma_coherent field in struct dev_archdata. Setting this from arch_setup_dma_ops() takes care of devices which set the dma-coherent property via device tree, and any PCI devices beneath a bridge described in DT, automatically. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14349/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
33 lines
813 B
C
33 lines
813 B
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
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*
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*/
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#ifndef __ASM_DMA_COHERENCE_H
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#define __ASM_DMA_COHERENCE_H
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enum coherent_io_user_state {
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IO_COHERENCE_DEFAULT,
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IO_COHERENCE_ENABLED,
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IO_COHERENCE_DISABLED,
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};
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#if defined(CONFIG_DMA_PERDEV_COHERENT)
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/* Don't provide (hw_)coherentio to avoid misuse */
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#elif defined(CONFIG_DMA_MAYBE_COHERENT)
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extern enum coherent_io_user_state coherentio;
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extern int hw_coherentio;
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#else
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#ifdef CONFIG_DMA_COHERENT
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#define coherentio IO_COHERENCE_ENABLED
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#else
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#define coherentio IO_COHERENCE_DISABLED
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#endif
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#define hw_coherentio 0
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#endif /* CONFIG_DMA_MAYBE_COHERENT */
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#endif
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