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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation version 2 of the license this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 83 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070034.021731668@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
173 lines
4.8 KiB
C
173 lines
4.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
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*/
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#ifndef ML26124_H
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#define ML26124_H
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/* Clock Control Register */
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#define ML26124_SMPLING_RATE 0x00
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#define ML26124_PLLNL 0x02
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#define ML26124_PLLNH 0x04
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#define ML26124_PLLML 0x06
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#define ML26124_PLLMH 0x08
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#define ML26124_PLLDIV 0x0a
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#define ML26124_CLK_EN 0x0c
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#define ML26124_CLK_CTL 0x0e
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/* System Control Register */
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#define ML26124_SW_RST 0x10
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#define ML26124_REC_PLYBAK_RUN 0x12
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#define ML26124_MIC_TIM 0x14
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/* Power Mnagement Register */
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#define ML26124_PW_REF_PW_MNG 0x20
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#define ML26124_PW_IN_PW_MNG 0x22
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#define ML26124_PW_DAC_PW_MNG 0x24
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#define ML26124_PW_SPAMP_PW_MNG 0x26
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#define ML26124_PW_LOUT_PW_MNG 0x28
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#define ML26124_PW_VOUT_PW_MNG 0x2a
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#define ML26124_PW_ZCCMP_PW_MNG 0x2e
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/* Analog Reference Control Register */
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#define ML26124_PW_MICBIAS_VOL 0x30
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/* Input/Output Amplifier Control Register */
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#define ML26124_PW_MIC_IN_VOL 0x32
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#define ML26124_PW_MIC_BOST_VOL 0x38
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#define ML26124_PW_SPK_AMP_VOL 0x3a
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#define ML26124_PW_AMP_VOL_FUNC 0x48
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#define ML26124_PW_AMP_VOL_FADE 0x4a
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/* Analog Path Control Register */
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#define ML26124_SPK_AMP_OUT 0x54
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#define ML26124_MIC_IF_CTL 0x5a
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#define ML26124_MIC_SELECT 0xe8
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/* Audio Interface Control Register */
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#define ML26124_SAI_TRANS_CTL 0x60
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#define ML26124_SAI_RCV_CTL 0x62
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#define ML26124_SAI_MODE_SEL 0x64
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/* DSP Control Register */
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#define ML26124_FILTER_EN 0x66
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#define ML26124_DVOL_CTL 0x68
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#define ML26124_MIXER_VOL_CTL 0x6a
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#define ML26124_RECORD_DIG_VOL 0x6c
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#define ML26124_PLBAK_DIG_VOL 0x70
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#define ML26124_DIGI_BOOST_VOL 0x72
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#define ML26124_EQ_GAIN_BRAND0 0x74
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#define ML26124_EQ_GAIN_BRAND1 0x76
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#define ML26124_EQ_GAIN_BRAND2 0x78
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#define ML26124_EQ_GAIN_BRAND3 0x7a
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#define ML26124_EQ_GAIN_BRAND4 0x7c
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#define ML26124_HPF2_CUTOFF 0x7e
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#define ML26124_EQBRAND0_F0L 0x80
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#define ML26124_EQBRAND0_F0H 0x82
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#define ML26124_EQBRAND0_F1L 0x84
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#define ML26124_EQBRAND0_F1H 0x86
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#define ML26124_EQBRAND1_F0L 0x88
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#define ML26124_EQBRAND1_F0H 0x8a
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#define ML26124_EQBRAND1_F1L 0x8c
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#define ML26124_EQBRAND1_F1H 0x8e
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#define ML26124_EQBRAND2_F0L 0x90
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#define ML26124_EQBRAND2_F0H 0x92
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#define ML26124_EQBRAND2_F1L 0x94
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#define ML26124_EQBRAND2_F1H 0x96
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#define ML26124_EQBRAND3_F0L 0x98
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#define ML26124_EQBRAND3_F0H 0x9a
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#define ML26124_EQBRAND3_F1L 0x9c
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#define ML26124_EQBRAND3_F1H 0x9e
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#define ML26124_EQBRAND4_F0L 0xa0
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#define ML26124_EQBRAND4_F0H 0xa2
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#define ML26124_EQBRAND4_F1L 0xa4
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#define ML26124_EQBRAND4_F1H 0xa6
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/* ALC Control Register */
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#define ML26124_ALC_MODE 0xb0
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#define ML26124_ALC_ATTACK_TIM 0xb2
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#define ML26124_ALC_DECAY_TIM 0xb4
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#define ML26124_ALC_HOLD_TIM 0xb6
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#define ML26124_ALC_TARGET_LEV 0xb8
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#define ML26124_ALC_MAXMIN_GAIN 0xba
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#define ML26124_NOIS_GATE_THRSH 0xbc
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#define ML26124_ALC_ZERO_TIMOUT 0xbe
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/* Playback Limiter Control Register */
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#define ML26124_PL_ATTACKTIME 0xc0
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#define ML26124_PL_DECAYTIME 0xc2
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#define ML26124_PL_TARGETTIME 0xc4
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#define ML26124_PL_MAXMIN_GAIN 0xc6
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#define ML26124_PLYBAK_BOST_VOL 0xc8
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#define ML26124_PL_0CROSS_TIMOUT 0xca
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/* Video Amplifer Control Register */
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#define ML26124_VIDEO_AMP_GAIN_CTL 0xd0
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#define ML26124_VIDEO_AMP_SETUP1 0xd2
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#define ML26124_VIDEO_AMP_CTL2 0xd4
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/* Clock select for machine driver */
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#define ML26124_USE_PLL 0
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#define ML26124_USE_MCLKI_256FS 1
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#define ML26124_USE_MCLKI_512FS 2
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#define ML26124_USE_MCLKI_1024FS 3
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/* Register Mask */
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#define ML26124_R0_MASK 0xf
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#define ML26124_R2_MASK 0xff
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#define ML26124_R4_MASK 0x1
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#define ML26124_R6_MASK 0xf
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#define ML26124_R8_MASK 0x3f
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#define ML26124_Ra_MASK 0x1f
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#define ML26124_Rc_MASK 0x1f
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#define ML26124_Re_MASK 0x7
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#define ML26124_R10_MASK 0x1
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#define ML26124_R12_MASK 0x17
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#define ML26124_R14_MASK 0x3f
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#define ML26124_R20_MASK 0x47
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#define ML26124_R22_MASK 0xa
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#define ML26124_R24_MASK 0x2
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#define ML26124_R26_MASK 0x1f
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#define ML26124_R28_MASK 0x2
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#define ML26124_R2a_MASK 0x2
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#define ML26124_R2e_MASK 0x2
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#define ML26124_R30_MASK 0x7
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#define ML26124_R32_MASK 0x3f
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#define ML26124_R38_MASK 0x38
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#define ML26124_R3a_MASK 0x3f
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#define ML26124_R48_MASK 0x3
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#define ML26124_R4a_MASK 0x7
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#define ML26124_R54_MASK 0x2a
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#define ML26124_R5a_MASK 0x3
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#define ML26124_Re8_MASK 0x3
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#define ML26124_R60_MASK 0xff
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#define ML26124_R62_MASK 0xff
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#define ML26124_R64_MASK 0x1
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#define ML26124_R66_MASK 0xff
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#define ML26124_R68_MASK 0x3b
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#define ML26124_R6a_MASK 0xf3
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#define ML26124_R6c_MASK 0xff
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#define ML26124_R70_MASK 0xff
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#define ML26124_MCLKEN BIT(0)
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#define ML26124_PLLEN BIT(1)
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#define ML26124_PLLOE BIT(2)
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#define ML26124_MCLKOE BIT(3)
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#define ML26124_BLT_ALL_ON 0x1f
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#define ML26124_BLT_PREAMP_ON 0x13
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#define ML26124_MICBEN_ON BIT(2)
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enum ml26124_regs {
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ML26124_MCLK = 0,
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};
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enum ml26124_clk_in {
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ML26124_USE_PLLOUT = 0,
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ML26124_USE_MCLKI,
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};
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#endif
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