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c1a3610104
In early stage of firmware SDK, DICE seems to lose its backward compatibility due to some registers on global address section. I found this with Alesis Multimix 12 FireWire with ancient firmware (approx. shipped version). According to retrieved log from the unit, global section has 96 byte space. On the other hand, current version of ALSA dice driver assumes that all of supported unit has at least 100 byte space. $ ./firewire-request /dev/fw1 read 0xffffe0000000 28 result: 000: 00 00 00 0a 00 00 00 18 00 00 00 22 00 00 00 8a result: 010: 00 00 00 ac 00 00 01 12 00 00 00 00 00 00 00 00 result: 020: 00 00 00 00 00 00 00 00 This commit adds support for the ancient firmware. Check of global section is loosened to accept the smaller space. The lack of information is already compensated by hard-coded parameters. I experienced that the latest version of Windows driver for this model can't handle this unit, too. This means that TCAT releases firmware SDK without backward compatibility for the ancient firmware. Below list is a early history of driver/firmware package released by Alesis. I investigated on wayback machine on Internet Archive: * Unknown: PAL v1.0.41.2, firmware v1.0.3 * Mar 2006: PAL v1.54.0, firmware v1.0.4 * Dec 2006: PAL v2.0.0.2, firmware v2.0 * Jun 2007: PAL v3.0.41.5, firmware v2.0 * Jul 2007: PAL v3.0.56.2. firmware v2.0 * Jan 2008: PAL v3.0.81.1080, firmware v2.0 If I can assume that firmware version is the same as DICE version, DICE version for the issued firmware may be v1.0.3. According to code base of userspace driver project (FFADO), I can read DICE v1.0.4 supports global space larger than 100 byte. I guess the smaller space of global section is a feature of DICE v1.0.3. Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Signed-off-by: Takashi Iwai <tiwai@suse.de>
379 lines
12 KiB
C
379 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef SOUND_FIREWIRE_DICE_INTERFACE_H_INCLUDED
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#define SOUND_FIREWIRE_DICE_INTERFACE_H_INCLUDED
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/*
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* DICE device interface definitions
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*/
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/*
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* Generally, all registers can be read like memory, i.e., with quadlet read or
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* block read transactions with at least quadlet-aligned offset and length.
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* Writes are not allowed except where noted; quadlet-sized registers must be
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* written with a quadlet write transaction.
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*
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* All values are in big endian. The DICE firmware runs on a little-endian CPU
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* and just byte-swaps _all_ quadlets on the bus, so values without endianness
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* (e.g. strings) get scrambled and must be byte-swapped again by the driver.
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*/
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/*
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* Streaming is handled by the "DICE driver" interface. Its registers are
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* located in this private address space.
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*/
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#define DICE_PRIVATE_SPACE 0xffffe0000000uLL
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/*
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* The registers are organized in several sections, which are organized
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* separately to allow them to be extended individually. Whether a register is
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* supported can be detected by checking its offset against its section's size.
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*
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* The section offset values are relative to DICE_PRIVATE_SPACE; the offset/
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* size values are measured in quadlets. Read-only.
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*/
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#define DICE_GLOBAL_OFFSET 0x00
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#define DICE_GLOBAL_SIZE 0x04
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#define DICE_TX_OFFSET 0x08
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#define DICE_TX_SIZE 0x0c
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#define DICE_RX_OFFSET 0x10
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#define DICE_RX_SIZE 0x14
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#define DICE_EXT_SYNC_OFFSET 0x18
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#define DICE_EXT_SYNC_SIZE 0x1c
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#define DICE_UNUSED2_OFFSET 0x20
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#define DICE_UNUSED2_SIZE 0x24
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/*
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* Global settings.
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*/
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/*
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* Stores the full 64-bit address (node ID and offset in the node's address
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* space) where the device will send notifications. Must be changed with
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* a compare/swap transaction by the owner. This register is automatically
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* cleared on a bus reset.
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*/
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#define GLOBAL_OWNER 0x000
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#define OWNER_NO_OWNER 0xffff000000000000uLL
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#define OWNER_NODE_SHIFT 48
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/*
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* A bitmask with asynchronous events; read-only. When any event(s) happen,
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* the bits of previous events are cleared, and the value of this register is
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* also written to the address stored in the owner register.
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*/
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#define GLOBAL_NOTIFICATION 0x008
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/* Some registers in the Rx/Tx sections may have changed. */
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#define NOTIFY_RX_CFG_CHG 0x00000001
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#define NOTIFY_TX_CFG_CHG 0x00000002
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/* Lock status of the current clock source may have changed. */
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#define NOTIFY_LOCK_CHG 0x00000010
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/* Write to the clock select register has been finished. */
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#define NOTIFY_CLOCK_ACCEPTED 0x00000020
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/* Lock status of some clock source has changed. */
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#define NOTIFY_EXT_STATUS 0x00000040
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/* Other bits may be used for device-specific events. */
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/*
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* A name that can be customized for each device; read/write. Padded with zero
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* bytes. Quadlets are byte-swapped. The encoding is whatever the host driver
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* happens to be using.
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*/
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#define GLOBAL_NICK_NAME 0x00c
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#define NICK_NAME_SIZE 64
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/*
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* The current sample rate and clock source; read/write. Whether a clock
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* source or sample rate is supported is device-specific; the internal clock
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* source is always available. Low/mid/high = up to 48/96/192 kHz. This
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* register can be changed even while streams are running.
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*/
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#define GLOBAL_CLOCK_SELECT 0x04c
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#define CLOCK_SOURCE_MASK 0x000000ff
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#define CLOCK_SOURCE_AES1 0x00000000
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#define CLOCK_SOURCE_AES2 0x00000001
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#define CLOCK_SOURCE_AES3 0x00000002
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#define CLOCK_SOURCE_AES4 0x00000003
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#define CLOCK_SOURCE_AES_ANY 0x00000004
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#define CLOCK_SOURCE_ADAT 0x00000005
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#define CLOCK_SOURCE_TDIF 0x00000006
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#define CLOCK_SOURCE_WC 0x00000007
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#define CLOCK_SOURCE_ARX1 0x00000008
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#define CLOCK_SOURCE_ARX2 0x00000009
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#define CLOCK_SOURCE_ARX3 0x0000000a
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#define CLOCK_SOURCE_ARX4 0x0000000b
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#define CLOCK_SOURCE_INTERNAL 0x0000000c
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#define CLOCK_RATE_MASK 0x0000ff00
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#define CLOCK_RATE_32000 0x00000000
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#define CLOCK_RATE_44100 0x00000100
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#define CLOCK_RATE_48000 0x00000200
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#define CLOCK_RATE_88200 0x00000300
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#define CLOCK_RATE_96000 0x00000400
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#define CLOCK_RATE_176400 0x00000500
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#define CLOCK_RATE_192000 0x00000600
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#define CLOCK_RATE_ANY_LOW 0x00000700
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#define CLOCK_RATE_ANY_MID 0x00000800
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#define CLOCK_RATE_ANY_HIGH 0x00000900
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#define CLOCK_RATE_NONE 0x00000a00
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#define CLOCK_RATE_SHIFT 8
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/*
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* Enable streaming; read/write. Writing a non-zero value (re)starts all
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* streams that have a valid iso channel set; zero stops all streams. The
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* streams' parameters must be configured before starting. This register is
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* automatically cleared on a bus reset.
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*/
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#define GLOBAL_ENABLE 0x050
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/*
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* Status of the sample clock; read-only.
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*/
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#define GLOBAL_STATUS 0x054
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/* The current clock source is locked. */
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#define STATUS_SOURCE_LOCKED 0x00000001
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/* The actual sample rate; CLOCK_RATE_32000-_192000 or _NONE. */
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#define STATUS_NOMINAL_RATE_MASK 0x0000ff00
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/*
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* Status of all clock sources; read-only.
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*/
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#define GLOBAL_EXTENDED_STATUS 0x058
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/*
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* The _LOCKED bits always show the current status; any change generates
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* a notification.
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*/
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#define EXT_STATUS_AES1_LOCKED 0x00000001
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#define EXT_STATUS_AES2_LOCKED 0x00000002
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#define EXT_STATUS_AES3_LOCKED 0x00000004
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#define EXT_STATUS_AES4_LOCKED 0x00000008
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#define EXT_STATUS_ADAT_LOCKED 0x00000010
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#define EXT_STATUS_TDIF_LOCKED 0x00000020
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#define EXT_STATUS_ARX1_LOCKED 0x00000040
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#define EXT_STATUS_ARX2_LOCKED 0x00000080
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#define EXT_STATUS_ARX3_LOCKED 0x00000100
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#define EXT_STATUS_ARX4_LOCKED 0x00000200
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#define EXT_STATUS_WC_LOCKED 0x00000400
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/*
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* The _SLIP bits do not generate notifications; a set bit indicates that an
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* error occurred since the last time when this register was read with
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* a quadlet read transaction.
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*/
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#define EXT_STATUS_AES1_SLIP 0x00010000
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#define EXT_STATUS_AES2_SLIP 0x00020000
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#define EXT_STATUS_AES3_SLIP 0x00040000
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#define EXT_STATUS_AES4_SLIP 0x00080000
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#define EXT_STATUS_ADAT_SLIP 0x00100000
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#define EXT_STATUS_TDIF_SLIP 0x00200000
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#define EXT_STATUS_ARX1_SLIP 0x00400000
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#define EXT_STATUS_ARX2_SLIP 0x00800000
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#define EXT_STATUS_ARX3_SLIP 0x01000000
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#define EXT_STATUS_ARX4_SLIP 0x02000000
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#define EXT_STATUS_WC_SLIP 0x04000000
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/*
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* The measured rate of the current clock source, in Hz; read-only.
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*/
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#define GLOBAL_SAMPLE_RATE 0x05c
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/*
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* Some old firmware versions do not have the following global registers.
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* Windows drivers produced by TCAT lost backward compatibility in its
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* early release because they can handle firmware only which supports the
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* following registers.
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*/
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/*
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* The version of the DICE driver specification that this device conforms to;
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* read-only.
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*/
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#define GLOBAL_VERSION 0x060
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/*
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* Supported sample rates and clock sources; read-only.
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*/
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#define GLOBAL_CLOCK_CAPABILITIES 0x064
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#define CLOCK_CAP_RATE_32000 0x00000001
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#define CLOCK_CAP_RATE_44100 0x00000002
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#define CLOCK_CAP_RATE_48000 0x00000004
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#define CLOCK_CAP_RATE_88200 0x00000008
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#define CLOCK_CAP_RATE_96000 0x00000010
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#define CLOCK_CAP_RATE_176400 0x00000020
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#define CLOCK_CAP_RATE_192000 0x00000040
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#define CLOCK_CAP_SOURCE_AES1 0x00010000
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#define CLOCK_CAP_SOURCE_AES2 0x00020000
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#define CLOCK_CAP_SOURCE_AES3 0x00040000
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#define CLOCK_CAP_SOURCE_AES4 0x00080000
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#define CLOCK_CAP_SOURCE_AES_ANY 0x00100000
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#define CLOCK_CAP_SOURCE_ADAT 0x00200000
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#define CLOCK_CAP_SOURCE_TDIF 0x00400000
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#define CLOCK_CAP_SOURCE_WC 0x00800000
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#define CLOCK_CAP_SOURCE_ARX1 0x01000000
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#define CLOCK_CAP_SOURCE_ARX2 0x02000000
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#define CLOCK_CAP_SOURCE_ARX3 0x04000000
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#define CLOCK_CAP_SOURCE_ARX4 0x08000000
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#define CLOCK_CAP_SOURCE_INTERNAL 0x10000000
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/*
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* Names of all clock sources; read-only. Quadlets are byte-swapped. Names
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* are separated with one backslash, the list is terminated with two
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* backslashes. Unused clock sources are included.
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*/
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#define GLOBAL_CLOCK_SOURCE_NAMES 0x068
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#define CLOCK_SOURCE_NAMES_SIZE 256
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/*
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* Capture stream settings. This section includes the number/size registers
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* and the registers of all streams.
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*/
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/*
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* The number of supported capture streams; read-only.
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*/
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#define TX_NUMBER 0x000
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/*
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* The size of one stream's register block, in quadlets; read-only. The
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* registers of the first stream follow immediately afterwards; the registers
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* of the following streams are offset by this register's value.
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*/
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#define TX_SIZE 0x004
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/*
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* The isochronous channel number on which packets are sent, or -1 if the
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* stream is not to be used; read/write.
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*/
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#define TX_ISOCHRONOUS 0x008
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/*
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* The number of audio channels; read-only. There will be one quadlet per
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* channel; the first channel is the first quadlet in a data block.
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*/
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#define TX_NUMBER_AUDIO 0x00c
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/*
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* The number of MIDI ports, 0-8; read-only. If > 0, there will be one
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* additional quadlet in each data block, following the audio quadlets.
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*/
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#define TX_NUMBER_MIDI 0x010
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/*
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* The speed at which the packets are sent, SCODE_100-_400; read/write.
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* SCODE_800 is only available in Dice III.
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*/
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#define TX_SPEED 0x014
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/*
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* Names of all audio channels; read-only. Quadlets are byte-swapped. Names
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* are separated with one backslash, the list is terminated with two
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* backslashes.
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*/
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#define TX_NAMES 0x018
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#define TX_NAMES_SIZE 256
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/*
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* Audio IEC60958 capabilities; read-only. Bitmask with one bit per audio
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* channel.
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*/
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#define TX_AC3_CAPABILITIES 0x118
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/*
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* Send audio data with IEC60958 label; read/write. Bitmask with one bit per
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* audio channel. This register can be changed even while the stream is
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* running.
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*/
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#define TX_AC3_ENABLE 0x11c
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/*
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* Playback stream settings. This section includes the number/size registers
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* and the registers of all streams.
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*/
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/*
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* The number of supported playback streams; read-only.
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*/
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#define RX_NUMBER 0x000
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/*
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* The size of one stream's register block, in quadlets; read-only. The
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* registers of the first stream follow immediately afterwards; the registers
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* of the following streams are offset by this register's value.
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*/
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#define RX_SIZE 0x004
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/*
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* The isochronous channel number on which packets are received, or -1 if the
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* stream is not to be used; read/write.
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*/
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#define RX_ISOCHRONOUS 0x008
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/*
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* Index of first quadlet to be interpreted; read/write. If > 0, that many
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* quadlets at the beginning of each data block will be ignored, and all the
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* audio and MIDI quadlets will follow.
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*/
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#define RX_SEQ_START 0x00c
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/*
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* The number of audio channels; read-only. There will be one quadlet per
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* channel.
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*/
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#define RX_NUMBER_AUDIO 0x010
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/*
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* The number of MIDI ports, 0-8; read-only. If > 0, there will be one
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* additional quadlet in each data block, following the audio quadlets.
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*/
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#define RX_NUMBER_MIDI 0x014
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/*
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* Names of all audio channels; read-only. Quadlets are byte-swapped. Names
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* are separated with one backslash, the list is terminated with two
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* backslashes.
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*/
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#define RX_NAMES 0x018
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#define RX_NAMES_SIZE 256
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/*
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* Audio IEC60958 capabilities; read-only. Bitmask with one bit per audio
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* channel.
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*/
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#define RX_AC3_CAPABILITIES 0x118
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/*
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* Receive audio data with IEC60958 label; read/write. Bitmask with one bit
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* per audio channel. This register can be changed even while the stream is
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* running.
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*/
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#define RX_AC3_ENABLE 0x11c
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/*
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* Extended synchronization information.
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* This section can be read completely with a block read request.
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*/
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/*
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* Current clock source; read-only.
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*/
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#define EXT_SYNC_CLOCK_SOURCE 0x000
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/*
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* Clock source is locked (boolean); read-only.
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*/
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#define EXT_SYNC_LOCKED 0x004
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/*
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* Current sample rate (CLOCK_RATE_* >> CLOCK_RATE_SHIFT), _32000-_192000 or
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* _NONE; read-only.
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*/
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#define EXT_SYNC_RATE 0x008
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/*
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* ADAT user data bits; read-only.
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*/
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#define EXT_SYNC_ADAT_USER_DATA 0x00c
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/* The data bits, if available. */
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#define ADAT_USER_DATA_MASK 0x0f
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/* The data bits are not available. */
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#define ADAT_USER_DATA_NO_DATA 0x10
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#endif
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