165 lines
5.5 KiB
C
165 lines
5.5 KiB
C
/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef __INCLUDE_MIPI_DSI_NORTHWEST_H
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#define __INCLUDE_MIPI_DSI_NORTHWEST_H
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/* ---------------------------- register offsets --------------------------- */
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/* sim */
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#define SIM_SOPT1 0x0
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#define MIPI_ISO_DISABLE 0x8
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#define SIM_SOPT1CFG 0x4
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#define DSI_RST_DPI_N 0x80000000
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#define DSI_RST_ESC_N 0x40000000
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#define DSI_RST_BYTE_N 0x20000000
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#define DSI_SD 0x200
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#define DSI_CM 0x100
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#define DSI_PLL_EN 0x80
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/* SRC */
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#define SRC_MIPIPHY_RCR 0x28
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#define MIPI_DSI_RESET_BYTE_N 0x2
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#define MIPI_DSI_RESET_N 0x4
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#define MIPI_DSI_DPI_RESET_N 0x8
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#define MIPI_DSI_ESC_RESET_N 0x10
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#define MIPI_DSI_PCLK_RESET_N 0x20
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/* GPR */
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#define IOMUXC_GPR_GPR13 0x34
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#define GPR_MIPI_MUX_SEL 0x4
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/* dphy */
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#define DPHY_PD_DPHY 0x300
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#define DPHY_M_PRG_HS_PREPARE 0x304
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#define DPHY_MC_PRG_HS_PREPARE 0x308
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#define DPHY_M_PRG_HS_ZERO 0x30c
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#define DPHY_MC_PRG_HS_ZERO 0x310
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#define DPHY_M_PRG_HS_TRAIL 0x314
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#define DPHY_MC_PRG_HS_TRAIL 0x318
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#define DPHY_PD_PLL 0x31c
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#define DPHY_TST 0x320
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#define DPHY_CN 0x324
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#define DPHY_CM 0x328
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#define DPHY_CO 0x32c
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#define DPHY_LOCK 0x330
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#define DPHY_LOCK_BYP 0x334
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#define DPHY_RTERM_SEL 0x338
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#define DPHY_AUTO_PD_EN 0x33c
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#define DPHY_RXLPRP 0x340
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#define DPHY_RXCDRP 0x344
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/* host */
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#define HOST_CFG_NUM_LANES 0x0
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#define HOST_CFG_NONCONTINUOUS_CLK 0x4
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#define HOST_CFG_T_PRE 0x8
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#define HOST_CFG_T_POST 0xc
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#define HOST_CFG_TX_GAP 0x10
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#define HOST_CFG_AUTOINSERT_EOTP 0x14
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#define HOST_CFG_EXTRA_CMDS_AFTER_EOTP 0x18
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#define HOST_CFG_HTX_TO_COUNT 0x1c
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#define HOST_CFG_LRX_H_TO_COUNT 0x20
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#define HOST_CFG_BTA_H_TO_COUNT 0x24
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#define HOST_CFG_TWAKEUP 0x28
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#define HOST_CFG_STATUS_OUT 0x2c
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#define HOST_RX_ERROR_STATUS 0x30
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/* dpi */
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#define DPI_PIXEL_PAYLOAD_SIZE 0x200
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#define DPI_PIXEL_FIFO_SEND_LEVEL 0x204
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#define DPI_INTERFACE_COLOR_CODING 0x208
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#define DPI_PIXEL_FORMAT 0x20c
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#define DPI_VSYNC_POLARITY 0x210
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#define DPI_HSYNC_POLARITY 0x214
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#define DPI_VIDEO_MODE 0x218
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#define DPI_HFP 0x21c
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#define DPI_HBP 0x220
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#define DPI_HSA 0x224
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#define DPI_ENABLE_MULT_PKTS 0x228
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#define DPI_VBP 0x22c
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#define DPI_VFP 0x230
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#define DPI_BLLP_MODE 0x234
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#define DPI_USE_NULL_PKT_BLLP 0x238
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#define DPI_VACTIVE 0x23c
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#define DPI_VC 0x240
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/* apb pkt */
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#define HOST_TX_PAYLOAD 0x280
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#define HOST_PKT_CONTROL 0x284
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#define HOST_PKT_CONTROL_WC(x) (((x) & 0xffff) << 0)
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#define HOST_PKT_CONTROL_VC(x) (((x) & 0x3) << 16)
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#define HOST_PKT_CONTROL_DT(x) (((x) & 0x3f) << 18)
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#define HOST_PKT_CONTROL_HS_SEL(x) (((x) & 0x1) << 24)
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#define HOST_PKT_CONTROL_BTA_TX(x) (((x) & 0x1) << 25)
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#define HOST_PKT_CONTROL_BTA_NO_TX(x) (((x) & 0x1) << 26)
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#define HOST_SEND_PACKET 0x288
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#define HOST_PKT_STATUS 0x28c
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#define HOST_PKT_FIFO_WR_LEVEL 0x290
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#define HOST_PKT_FIFO_RD_LEVEL 0x294
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#define HOST_PKT_RX_PAYLOAD 0x298
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#define HOST_PKT_RX_PKT_HEADER 0x29c
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#define HOST_PKT_RX_PKT_HEADER_WC(x) (((x) & 0xffff) << 0)
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#define HOST_PKT_RX_PKT_HEADER_DT(x) (((x) & 0x3f) << 16)
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#define HOST_PKT_RX_PKT_HEADER_VC(x) (((x) & 0x3) << 22)
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#define HOST_IRQ_STATUS 0x2a0
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#define HOST_IRQ_STATUS_SM_NOT_IDLE (1 << 0)
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#define HOST_IRQ_STATUS_TX_PKT_DONE (1 << 1)
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#define HOST_IRQ_STATUS_DPHY_DIRECTION (1 << 2)
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#define HOST_IRQ_STATUS_TX_FIFO_OVFLW (1 << 3)
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#define HOST_IRQ_STATUS_TX_FIFO_UDFLW (1 << 4)
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#define HOST_IRQ_STATUS_RX_FIFO_OVFLW (1 << 5)
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#define HOST_IRQ_STATUS_RX_FIFO_UDFLW (1 << 6)
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#define HOST_IRQ_STATUS_RX_PKT_HDR_RCVD (1 << 7)
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#define HOST_IRQ_STATUS_RX_PKT_PAYLOAD_DATA_RCVD (1 << 8)
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#define HOST_IRQ_STATUS_HOST_BTA_TIMEOUT (1 << 29)
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#define HOST_IRQ_STATUS_LP_RX_TIMEOUT (1 << 30)
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#define HOST_IRQ_STATUS_HS_TX_TIMEOUT (1 << 31)
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#define HOST_IRQ_STATUS2 0x2a4
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#define HOST_IRQ_STATUS2_SINGLE_BIT_ECC_ERR (1 << 0)
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#define HOST_IRQ_STATUS2_MULTI_BIT_ECC_ERR (1 << 1)
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#define HOST_IRQ_STATUS2_CRC_ERR (1 << 2)
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#define HOST_IRQ_MASK 0x2a8
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#define HOST_IRQ_MASK_SM_NOT_IDLE_MASK (1 << 0)
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#define HOST_IRQ_MASK_TX_PKT_DONE_MASK (1 << 1)
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#define HOST_IRQ_MASK_DPHY_DIRECTION_MASK (1 << 2)
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#define HOST_IRQ_MASK_TX_FIFO_OVFLW_MASK (1 << 3)
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#define HOST_IRQ_MASK_TX_FIFO_UDFLW_MASK (1 << 4)
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#define HOST_IRQ_MASK_RX_FIFO_OVFLW_MASK (1 << 5)
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#define HOST_IRQ_MASK_RX_FIFO_UDFLW_MASK (1 << 6)
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#define HOST_IRQ_MASK_RX_PKT_HDR_RCVD_MASK (1 << 7)
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#define HOST_IRQ_MASK_RX_PKT_PAYLOAD_DATA_RCVD_MASK (1 << 8)
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#define HOST_IRQ_MASK_HOST_BTA_TIMEOUT_MASK (1 << 29)
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#define HOST_IRQ_MASK_LP_RX_TIMEOUT_MASK (1 << 30)
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#define HOST_IRQ_MASK_HS_TX_TIMEOUT_MASK (1 << 31)
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#define HOST_IRQ_MASK2 0x2ac
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#define HOST_IRQ_MASK2_SINGLE_BIT_ECC_ERR_MASK (1 << 0)
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#define HOST_IRQ_MASK2_MULTI_BIT_ECC_ERR_MASK (1 << 1)
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#define HOST_IRQ_MASK2_CRC_ERR_MASK (1 << 2)
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/* ------------------------------------- end -------------------------------- */
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#endif
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