330 lines
7.8 KiB
C
330 lines
7.8 KiB
C
/*
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* Copyright 2017-2020 NXP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy/phy.h>
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#include <linux/phy/phy-mixel-lvds.h>
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#include <linux/platform_device.h>
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#define SET 0x4
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#define CLR 0x8
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#define TOG 0xc
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#define PHY_CTRL 0x0
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#define M(n) (((n) & 0x3) << 17)
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#define M_MASK 0x60000
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#define CCM(n) (((n) & 0x7) << 14)
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#define CCM_MASK 0x1c000
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#define CA(n) (((n) & 0x7) << 11)
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#define CA_MASK 0x3800
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#define TST(n) (((n) & 0x3f) << 5)
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#define TST_MASK 0x7e0
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#define CH_EN(id) BIT(3 + (id))
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#define NB BIT(2)
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#define RFB BIT(1)
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#define PD BIT(0)
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#define PHY_STATUS 0x10
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#define LOCK BIT(0)
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#define PHY_SS_CTRL 0x20
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#define CH_HSYNC_M(id) BIT(0 + ((id) * 2))
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#define CH_VSYNC_M(id) BIT(1 + ((id) * 2))
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#define CH_PHSYNC(id) BIT(0 + ((id) * 2))
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#define CH_PVSYNC(id) BIT(1 + ((id) * 2))
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struct mixel_lvds_phy {
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struct phy *phy;
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unsigned int id;
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};
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struct mixel_lvds_phy_priv {
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struct device *dev;
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void __iomem *base;
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struct mutex lock;
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struct clk *phy_clk;
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struct mixel_lvds_phy *phys[2];
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};
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static inline u32 phy_read(struct phy *phy, unsigned int reg)
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{
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struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
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return readl(priv->base + reg);
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}
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static inline void phy_write(struct phy *phy, unsigned int reg, u32 value)
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{
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struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
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writel(value, priv->base + reg);
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}
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void mixel_phy_lvds_set_phy_speed(struct phy *phy, unsigned long phy_clk_rate)
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{
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struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
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u32 val;
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phy_pm_runtime_get_sync(phy);
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/* assuming NB is zero - 7bits per channel */
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clk_prepare_enable(priv->phy_clk);
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mutex_lock(&priv->lock);
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val = phy_read(phy, PHY_CTRL);
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val &= ~M_MASK;
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if (phy_clk_rate < 44000000)
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val |= M(0x2);
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else if (phy_clk_rate < 90000000)
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val |= M(0x1);
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else
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val |= M(0x0);
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phy_write(phy, PHY_CTRL, val);
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mutex_unlock(&priv->lock);
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clk_disable_unprepare(priv->phy_clk);
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clk_set_rate(priv->phy_clk, phy_clk_rate);
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phy_pm_runtime_put(phy);
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}
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EXPORT_SYMBOL_GPL(mixel_phy_lvds_set_phy_speed);
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void mixel_phy_lvds_set_hsync_pol(struct phy *phy, bool active_high)
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{
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struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
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struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
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unsigned int id = lvds_phy->id;
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u32 val;
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phy_pm_runtime_get_sync(phy);
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clk_prepare_enable(priv->phy_clk);
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mutex_lock(&priv->lock);
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val = phy_read(phy, PHY_SS_CTRL);
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val &= ~CH_HSYNC_M(id);
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if (active_high)
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val |= CH_PHSYNC(id);
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phy_write(phy, PHY_SS_CTRL, val);
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mutex_unlock(&priv->lock);
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clk_disable_unprepare(priv->phy_clk);
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phy_pm_runtime_put(phy);
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}
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EXPORT_SYMBOL_GPL(mixel_phy_lvds_set_hsync_pol);
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void mixel_phy_lvds_set_vsync_pol(struct phy *phy, bool active_high)
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{
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struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
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struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
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unsigned int id = lvds_phy->id;
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u32 val;
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phy_pm_runtime_get_sync(phy);
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clk_prepare_enable(priv->phy_clk);
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mutex_lock(&priv->lock);
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val = phy_read(phy, PHY_SS_CTRL);
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val &= ~CH_VSYNC_M(id);
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if (active_high)
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val |= CH_PVSYNC(id);
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phy_write(phy, PHY_SS_CTRL, val);
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mutex_unlock(&priv->lock);
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clk_disable_unprepare(priv->phy_clk);
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phy_pm_runtime_put(phy);
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}
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EXPORT_SYMBOL_GPL(mixel_phy_lvds_set_vsync_pol);
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static int mixel_lvds_phy_init(struct phy *phy)
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{
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struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
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u32 val;
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clk_prepare_enable(priv->phy_clk);
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mutex_lock(&priv->lock);
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val = phy_read(phy, PHY_CTRL);
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val &= ~(M_MASK | CCM_MASK | CA_MASK | TST_MASK | NB | PD);
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val |= (M(0x0) | CCM(0x5) | CA(0x4) | TST(0x25) | RFB);
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phy_write(phy, PHY_CTRL, val);
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mutex_unlock(&priv->lock);
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clk_disable_unprepare(priv->phy_clk);
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return 0;
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}
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static int mixel_lvds_phy_power_on(struct phy *phy)
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{
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struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
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struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
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unsigned int id = lvds_phy->id;
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clk_prepare_enable(priv->phy_clk);
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mutex_lock(&priv->lock);
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phy_write(phy, PHY_CTRL + SET, CH_EN(id));
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mutex_unlock(&priv->lock);
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usleep_range(500, 1000);
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return 0;
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}
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static int mixel_lvds_phy_power_off(struct phy *phy)
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{
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struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
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struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
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unsigned int id = lvds_phy->id;
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mutex_lock(&priv->lock);
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phy_write(phy, PHY_CTRL + CLR, CH_EN(id));
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mutex_unlock(&priv->lock);
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clk_disable_unprepare(priv->phy_clk);
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return 0;
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}
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static const struct phy_ops mixel_lvds_phy_ops = {
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.init = mixel_lvds_phy_init,
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.power_on = mixel_lvds_phy_power_on,
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.power_off = mixel_lvds_phy_power_off,
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.owner = THIS_MODULE,
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};
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static int mixel_lvds_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct device_node *child;
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struct resource *res;
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struct phy_provider *phy_provider;
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struct mixel_lvds_phy_priv *priv;
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struct mixel_lvds_phy *lvds_phy;
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struct phy *phy;
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u32 phy_id;
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int ret;
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if (!np)
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return -ENODEV;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENODEV;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->base = devm_ioremap(dev, res->start, SZ_256);
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if (!priv->base)
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return -ENOMEM;
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priv->dev = dev;
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priv->phy_clk = devm_clk_get(dev, "phy");
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if (IS_ERR(priv->phy_clk)) {
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dev_err(dev, "cannot get phy clock\n");
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return PTR_ERR(priv->phy_clk);
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}
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mutex_init(&priv->lock);
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dev_set_drvdata(dev, priv);
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pm_runtime_enable(dev);
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for_each_available_child_of_node(np, child) {
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if (of_property_read_u32(child, "reg", &phy_id)) {
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dev_err(dev, "missing reg property in node %s\n",
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child->name);
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ret = -EINVAL;
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goto put_child;
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}
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if (phy_id >= ARRAY_SIZE(priv->phys)) {
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dev_err(dev, "invalid reg in node %s\n", child->name);
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ret = -EINVAL;
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goto put_child;
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}
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if (priv->phys[phy_id]) {
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dev_err(dev, "duplicated phy id: %u\n", phy_id);
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ret = -EINVAL;
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goto put_child;
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}
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lvds_phy = devm_kzalloc(dev, sizeof(*lvds_phy), GFP_KERNEL);
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if (!lvds_phy) {
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ret = -ENOMEM;
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goto put_child;
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}
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phy = devm_phy_create(dev, child, &mixel_lvds_phy_ops);
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if (IS_ERR(phy)) {
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dev_err(dev, "failed to create phy\n");
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ret = PTR_ERR(phy);
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goto put_child;
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}
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lvds_phy->phy = phy;
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lvds_phy->id = phy_id;
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priv->phys[phy_id] = lvds_phy;
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phy_set_drvdata(phy, lvds_phy);
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}
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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if (IS_ERR(phy_provider)) {
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pm_runtime_disable(dev);
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return PTR_ERR(phy_provider);
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}
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return 0;
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put_child:
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of_node_put(child);
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pm_runtime_disable(dev);
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return ret;
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}
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static int mixel_lvds_phy_remove(struct platform_device *pdev)
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{
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pm_runtime_disable(&pdev->dev);
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return 0;
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}
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static const struct of_device_id mixel_lvds_phy_of_match[] = {
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{ .compatible = "mixel,lvds-phy" },
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{}
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};
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MODULE_DEVICE_TABLE(of, mixel_lvds_phy_of_match);
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static struct platform_driver mixel_lvds_phy_driver = {
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.probe = mixel_lvds_phy_probe,
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.remove = mixel_lvds_phy_remove,
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.driver = {
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.name = "mixel-lvds-phy",
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.of_match_table = mixel_lvds_phy_of_match,
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}
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};
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module_platform_driver(mixel_lvds_phy_driver);
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MODULE_AUTHOR("NXP Semiconductor");
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MODULE_DESCRIPTION("Mixel LVDS PHY driver");
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MODULE_LICENSE("GPL v2");
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