318 lines
7.9 KiB
C
318 lines
7.9 KiB
C
/*
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* Copyright 2017 NXP
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/of_platform.h>
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#include <linux/spinlock.h>
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#include <linux/pm_runtime.h>
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#define CHANCSR(n) (0x0 + 0x40 * n)
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#define CHANVEC(n) (0x4 + 0x40 * n)
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#define CHANIER(n) (0x10 + (0x40 * n))
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#define CHANIPR(n) (0x20 + (0x40 * n))
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struct intmux_irqchip_data {
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struct irq_chip chip;
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int chanidx;
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int irq;
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struct irq_domain *domain;
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unsigned long irqstat;
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};
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struct intmux_data {
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spinlock_t lock;
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struct platform_device *pdev;
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void __iomem *regs;
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struct clk *ipg_clk;
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int channum;
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#ifdef CONFIG_PM
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u32 *saved_reg;
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#endif
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struct intmux_irqchip_data irqchip_data[];
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};
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static void imx_intmux_irq_unmask(struct irq_data *d)
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{
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struct intmux_irqchip_data *irqchip_data = d->chip_data;
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u32 idx = irqchip_data->chanidx;
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struct intmux_data *intmux_data = container_of(irqchip_data, struct intmux_data, irqchip_data[idx]);
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void __iomem *reg;
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u32 val;
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spin_lock(&intmux_data->lock);
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reg = intmux_data->regs + CHANIER(idx);
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val = readl_relaxed(reg);
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val |= 1 << d->hwirq;
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writel_relaxed(val, reg);
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spin_unlock(&intmux_data->lock);
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}
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static void imx_intmux_irq_mask(struct irq_data *d)
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{
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struct intmux_irqchip_data *irqchip_data = d->chip_data;
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u32 idx = irqchip_data->chanidx;
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struct intmux_data *intmux_data = container_of(irqchip_data, struct intmux_data, irqchip_data[idx]);
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void __iomem *reg;
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u32 val;
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spin_lock(&intmux_data->lock);
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reg = intmux_data->regs + CHANIER(idx);
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val = readl_relaxed(reg);
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val &= ~(1 << d->hwirq);
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writel_relaxed(val, reg);
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spin_unlock(&intmux_data->lock);
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}
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static void imx_intmux_irq_ack(struct irq_data *d)
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{
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/* the irqchip has no ack */
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}
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static struct irq_chip imx_intmux_irq_chip = {
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.name = "intmux",
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.irq_eoi = irq_chip_eoi_parent,
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.irq_mask = imx_intmux_irq_mask,
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.irq_unmask = imx_intmux_irq_unmask,
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.irq_ack = imx_intmux_irq_ack,
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};
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static int imx_intmux_irq_map(struct irq_domain *h, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct intmux_irqchip_data *irqchip_data = h->host_data;
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irq_set_chip_data(irq, h->host_data);
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irq_set_chip_and_handler(irq, &irqchip_data->chip, handle_edge_irq);
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return 0;
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}
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static const struct irq_domain_ops imx_intmux_domain_ops = {
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.map = imx_intmux_irq_map,
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.xlate = irq_domain_xlate_twocell,
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};
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static void imx_intmux_update_irqstat(struct intmux_irqchip_data *irqchip_data)
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{
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int i = irqchip_data->chanidx;
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struct intmux_data *intmux_data = container_of(irqchip_data, struct intmux_data, irqchip_data[i]);
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irqchip_data->irqstat = readl_relaxed(intmux_data->regs + CHANIPR(i));
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}
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static void imx_intmux_irq_handler(struct irq_desc *desc)
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{
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struct intmux_irqchip_data *irqchip_data = irq_desc_get_handler_data(desc);
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int pos, virq;
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chained_irq_enter(irq_desc_get_chip(desc), desc);
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imx_intmux_update_irqstat(irqchip_data);
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for_each_set_bit(pos, &irqchip_data->irqstat, 32) {
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virq = irq_find_mapping(irqchip_data->domain, pos);
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if (virq)
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generic_handle_irq(virq);
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}
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chained_irq_exit(irq_desc_get_chip(desc), desc);
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}
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static int imx_intmux_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct intmux_data *intmux_data;
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struct resource *res;
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int i;
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int channum;
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int ret;
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ret = of_property_read_u32(np, "nxp,intmux_chans", &channum);
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if (ret)
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channum = 1;
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intmux_data = devm_kzalloc(&pdev->dev, sizeof(*intmux_data) +
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channum *
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sizeof(intmux_data->irqchip_data[0]),
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GFP_KERNEL);
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if (!intmux_data)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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intmux_data->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(intmux_data->regs)) {
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dev_err(&pdev->dev, "failed to initialize reg\n");
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return PTR_ERR(intmux_data->regs);
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}
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intmux_data->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
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if (IS_ERR(intmux_data->ipg_clk)) {
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ret = PTR_ERR(intmux_data->ipg_clk);
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dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
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return ret;
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}
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intmux_data->channum = channum;
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intmux_data->pdev = pdev;
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spin_lock_init(&intmux_data->lock);
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if (IS_ENABLED(CONFIG_PM)) {
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/* save CHANIER register */
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intmux_data->saved_reg = devm_kzalloc(&pdev->dev,
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sizeof(u32) * channum,
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GFP_KERNEL);
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if (!intmux_data->saved_reg)
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return -ENOMEM;
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}
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for (i = 0; i < channum; i++) {
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intmux_data->irqchip_data[i].chip = imx_intmux_irq_chip;
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intmux_data->irqchip_data[i].chip.parent_device = &pdev->dev;
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intmux_data->irqchip_data[i].chanidx = i;
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intmux_data->irqchip_data[i].irq = platform_get_irq(pdev, i);
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if (intmux_data->irqchip_data[i].irq <= 0) {
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dev_err(&pdev->dev, "failed to get irq\n");
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return -ENODEV;
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}
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intmux_data->irqchip_data[i].domain = irq_domain_add_linear(np,
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32,
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&imx_intmux_domain_ops,
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&intmux_data->irqchip_data[i]);
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if (!intmux_data->irqchip_data[i].domain) {
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dev_err(&intmux_data->pdev->dev,
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"failed to create IRQ domain\n");
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return -ENOMEM;
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}
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irq_set_chained_handler_and_data(intmux_data->irqchip_data[i].irq,
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imx_intmux_irq_handler,
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&intmux_data->irqchip_data[i]);
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}
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platform_set_drvdata(pdev, intmux_data);
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pm_runtime_get_noresume(&pdev->dev);
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pm_runtime_set_active(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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ret = clk_prepare_enable(intmux_data->ipg_clk);
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if (ret) {
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dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
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return ret;
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}
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/*
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* Let pm_runtime_put() disable clock.
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* If CONFIG_PM is not enabled, the clock will stay powered.
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*/
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pm_runtime_put(&pdev->dev);
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return 0;
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}
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static int imx_intmux_remove(struct platform_device *pdev)
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{
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struct intmux_data *intmux_data = platform_get_drvdata(pdev);
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int i;
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for (i = 0; i < intmux_data->channum; i++) {
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irq_set_chained_handler_and_data(intmux_data->irqchip_data[i].irq, NULL, NULL);
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irq_domain_remove(intmux_data->irqchip_data[i].domain);
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}
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platform_set_drvdata(pdev, NULL);
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pm_runtime_disable(&pdev->dev);
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return 0;
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}
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#ifdef CONFIG_PM
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static void imx_intmux_save_regs(struct intmux_data *intmux_data)
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{
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int i;
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for (i = 0; i < intmux_data->channum; i++)
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intmux_data->saved_reg[i] = readl_relaxed(intmux_data->regs
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+ CHANIER(i));
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}
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static void imx_intmux_restore_regs(struct intmux_data *intmux_data)
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{
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int i;
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for (i = 0; i < intmux_data->channum; i++)
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writel_relaxed(intmux_data->saved_reg[i], intmux_data->regs
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+ CHANIER(i));
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}
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static int imx_intmux_runtime_suspend(struct device *dev)
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{
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struct intmux_data *intmux_data = dev_get_drvdata(dev);
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imx_intmux_save_regs(intmux_data);
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clk_disable_unprepare(intmux_data->ipg_clk);
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return 0;
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}
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static int imx_intmux_runtime_resume(struct device *dev)
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{
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struct intmux_data *intmux_data = dev_get_drvdata(dev);
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int ret;
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ret = clk_prepare_enable(intmux_data->ipg_clk);
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if (ret) {
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dev_err(dev, "failed to enable ipg clk: %d\n", ret);
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return ret;
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}
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imx_intmux_restore_regs(intmux_data);
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return 0;
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}
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#endif
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static const struct dev_pm_ops imx_intmux_pm_ops = {
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SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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pm_runtime_force_resume)
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SET_RUNTIME_PM_OPS(imx_intmux_runtime_suspend,
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imx_intmux_runtime_resume, NULL)
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};
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static const struct of_device_id imx_intmux_id[] = {
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{ .compatible = "nxp,imx-intmux", },
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{},
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};
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static struct platform_driver imx_intmux_driver = {
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.driver = {
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.name = "imx-intmux",
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.of_match_table = imx_intmux_id,
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.pm = &imx_intmux_pm_ops,
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},
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.probe = imx_intmux_probe,
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.remove = imx_intmux_remove,
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};
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static int __init irq_imx_intmux_init(void)
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{
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return platform_driver_register(&imx_intmux_driver);
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}
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arch_initcall(irq_imx_intmux_init);
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MODULE_AUTHOR("NXP Semiconductor");
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MODULE_DESCRIPTION("NXP i.MX8 irq steering driver");
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MODULE_LICENSE("GPL v2");
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