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c8c4076723
Recent Intel chipsets including Skylake and ApolloLake have a special ITSSPRC register which allows the 8254 PIT to be gated. When gated, the 8254 registers can still be programmed as normal, but there are no IRQ0 timer interrupts. Some products such as the Connex L1430 and exone go Rugged E11 use this register to ship with the PIT gated by default. This causes Linux to fail to boot: Kernel panic - not syncing: IO-APIC + timer doesn't work! Boot with apic=debug and send a report. The panic happens before the framebuffer is initialized, so to the user, it appears as an early boot hang on a black screen. Affected products typically have a BIOS option that can be used to enable the 8254 and make Linux work (Chipset -> South Cluster Configuration -> Miscellaneous Configuration -> 8254 Clock Gating), however it would be best to make Linux support the no-8254 case. Modern sytems allow to discover the TSC and local APIC timer frequencies, so the calibration against the PIT is not required. These systems have always running timers and the local APIC timer works also in deep power states. So the setup of the PIT including the IO-APIC timer interrupt delivery checks are a pointless exercise. Skip the PIT setup and the IO-APIC timer interrupt checks on these systems, which avoids the panic caused by non ticking PITs and also speeds up the boot process. Thanks to Daniel for providing the changelog, initial analysis of the problem and testing against a variety of machines. Reported-by: Daniel Drake <drake@endlessm.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Daniel Drake <drake@endlessm.com> Cc: bp@alien8.de Cc: hpa@zytor.com Cc: linux@endlessm.com Cc: rafael.j.wysocki@intel.com Cc: hdegoede@redhat.com Link: https://lkml.kernel.org/r/20190628072307.24678-1-drake@endlessm.com
68 lines
1.6 KiB
C
68 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* 8253/PIT functions
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*
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*/
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#include <linux/clockchips.h>
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#include <linux/init.h>
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#include <linux/timex.h>
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#include <linux/i8253.h>
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#include <asm/apic.h>
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#include <asm/hpet.h>
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#include <asm/time.h>
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#include <asm/smp.h>
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/*
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* HPET replaces the PIT, when enabled. So we need to know, which of
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* the two timers is used
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*/
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struct clock_event_device *global_clock_event;
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/*
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* Modern chipsets can disable the PIT clock which makes it unusable. It
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* would be possible to enable the clock but the registers are chipset
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* specific and not discoverable. Avoid the whack a mole game.
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*
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* These platforms have discoverable TSC/CPU frequencies but this also
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* requires to know the local APIC timer frequency as it normally is
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* calibrated against the PIT interrupt.
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*/
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static bool __init use_pit(void)
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{
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if (!IS_ENABLED(CONFIG_X86_TSC) || !boot_cpu_has(X86_FEATURE_TSC))
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return true;
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/* This also returns true when APIC is disabled */
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return apic_needs_pit();
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}
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bool __init pit_timer_init(void)
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{
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if (!use_pit())
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return false;
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clockevent_i8253_init(true);
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global_clock_event = &i8253_clockevent;
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return true;
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}
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#ifndef CONFIG_X86_64
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static int __init init_pit_clocksource(void)
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{
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/*
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* Several reasons not to register PIT as a clocksource:
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*
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* - On SMP PIT does not scale due to i8253_lock
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* - when HPET is enabled
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* - when local APIC timer is active (PIT is switched off)
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*/
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if (num_possible_cpus() > 1 || is_hpet_enabled() ||
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!clockevent_state_periodic(&i8253_clockevent))
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return 0;
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return clocksource_i8253_init();
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}
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arch_initcall(init_pit_clocksource);
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#endif /* !CONFIG_X86_64 */
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