mirror of
https://github.com/brain-hackers/linux-brain.git
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42dac16dc4
[ Upstream commit 23eb7f560a2a6a1b0dbaaaae8685da75314347e4 ]
Similar to commit 22e9c88d48
("powerpc/64: reuse PPC32 static inline flush_dcache_range()")
this patch converts the following ASM symbols to C:
flush_icache_range()
__flush_dcache_icache()
__flush_dcache_icache_phys()
This was done as we discovered a long-standing bug where the length of the
range was truncated due to using a 32 bit shift instead of a 64 bit one.
By converting these functions to C, it becomes easier to maintain.
flush_dcache_icache_phys() retains a critical assembler section as we must
ensure there are no memory accesses while the data MMU is disabled
(authored by Christophe Leroy). Since this has no external callers, it has
also been made static, allowing the compiler to inline it within
flush_dcache_icache_page().
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
[mpe: Minor fixups, don't export __flush_dcache_icache()]
Link: https://lore.kernel.org/r/20191104023305.9581-5-alastair@au1.ibm.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
982 lines
20 KiB
ArmAsm
982 lines
20 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* This file contains miscellaneous low-level functions.
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
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* and Paul Mackerras.
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*
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* kexec bits:
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* Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com>
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* GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
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* PPC44x port. Copyright (C) 2011, IBM Corporation
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* Author: Suzuki Poulose <suzuki@in.ibm.com>
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*/
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#include <linux/sys.h>
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#include <asm/unistd.h>
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#include <asm/errno.h>
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/cache.h>
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#include <asm/cputable.h>
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#include <asm/mmu.h>
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#include <asm/ppc_asm.h>
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#include <asm/thread_info.h>
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#include <asm/asm-offsets.h>
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#include <asm/processor.h>
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#include <asm/kexec.h>
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#include <asm/bug.h>
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#include <asm/ptrace.h>
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#include <asm/export.h>
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#include <asm/feature-fixups.h>
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.text
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/*
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* We store the saved ksp_limit in the unused part
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* of the STACK_FRAME_OVERHEAD
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*/
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_GLOBAL(call_do_softirq)
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mflr r0
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stw r0,4(r1)
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lwz r10,THREAD+KSP_LIMIT(r2)
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stw r3, THREAD+KSP_LIMIT(r2)
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stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
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mr r1,r3
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stw r10,8(r1)
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bl __do_softirq
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lwz r10,8(r1)
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lwz r1,0(r1)
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lwz r0,4(r1)
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stw r10,THREAD+KSP_LIMIT(r2)
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mtlr r0
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blr
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/*
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* void call_do_irq(struct pt_regs *regs, void *sp);
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*/
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_GLOBAL(call_do_irq)
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mflr r0
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stw r0,4(r1)
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lwz r10,THREAD+KSP_LIMIT(r2)
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stw r4, THREAD+KSP_LIMIT(r2)
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stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
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mr r1,r4
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stw r10,8(r1)
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bl __do_irq
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lwz r10,8(r1)
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lwz r1,0(r1)
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lwz r0,4(r1)
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stw r10,THREAD+KSP_LIMIT(r2)
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mtlr r0
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blr
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/*
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* This returns the high 64 bits of the product of two 64-bit numbers.
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*/
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_GLOBAL(mulhdu)
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cmpwi r6,0
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cmpwi cr1,r3,0
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mr r10,r4
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mulhwu r4,r4,r5
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beq 1f
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mulhwu r0,r10,r6
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mullw r7,r10,r5
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addc r7,r0,r7
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addze r4,r4
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1: beqlr cr1 /* all done if high part of A is 0 */
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mullw r9,r3,r5
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mulhwu r10,r3,r5
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beq 2f
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mullw r0,r3,r6
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mulhwu r8,r3,r6
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addc r7,r0,r7
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adde r4,r4,r8
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addze r10,r10
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2: addc r4,r4,r9
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addze r3,r10
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blr
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/*
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* reloc_got2 runs through the .got2 section adding an offset
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* to each entry.
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*/
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_GLOBAL(reloc_got2)
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mflr r11
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lis r7,__got2_start@ha
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addi r7,r7,__got2_start@l
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lis r8,__got2_end@ha
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addi r8,r8,__got2_end@l
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subf r8,r7,r8
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srwi. r8,r8,2
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beqlr
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mtctr r8
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bl 1f
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1: mflr r0
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lis r4,1b@ha
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addi r4,r4,1b@l
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subf r0,r4,r0
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add r7,r0,r7
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2: lwz r0,0(r7)
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add r0,r0,r3
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stw r0,0(r7)
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addi r7,r7,4
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bdnz 2b
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mtlr r11
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blr
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/*
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* call_setup_cpu - call the setup_cpu function for this cpu
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* r3 = data offset, r24 = cpu number
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*
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* Setup function is called with:
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* r3 = data offset
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* r4 = ptr to CPU spec (relocated)
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*/
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_GLOBAL(call_setup_cpu)
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addis r4,r3,cur_cpu_spec@ha
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addi r4,r4,cur_cpu_spec@l
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lwz r4,0(r4)
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add r4,r4,r3
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lwz r5,CPU_SPEC_SETUP(r4)
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cmpwi 0,r5,0
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add r5,r5,r3
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beqlr
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mtctr r5
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bctr
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#if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_PPC_BOOK3S_32)
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/* This gets called by via-pmu.c to switch the PLL selection
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* on 750fx CPU. This function should really be moved to some
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* other place (as most of the cpufreq code in via-pmu
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*/
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_GLOBAL(low_choose_750fx_pll)
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/* Clear MSR:EE */
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mfmsr r7
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rlwinm r0,r7,0,17,15
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mtmsr r0
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/* If switching to PLL1, disable HID0:BTIC */
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cmplwi cr0,r3,0
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beq 1f
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mfspr r5,SPRN_HID0
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rlwinm r5,r5,0,27,25
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sync
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mtspr SPRN_HID0,r5
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isync
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sync
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1:
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/* Calc new HID1 value */
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mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
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rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
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rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
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or r4,r4,r5
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mtspr SPRN_HID1,r4
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#ifdef CONFIG_SMP
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/* Store new HID1 image */
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lwz r6,TASK_CPU(r2)
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slwi r6,r6,2
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#else
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li r6, 0
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#endif
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addis r6,r6,nap_save_hid1@ha
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stw r4,nap_save_hid1@l(r6)
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/* If switching to PLL0, enable HID0:BTIC */
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cmplwi cr0,r3,0
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bne 1f
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mfspr r5,SPRN_HID0
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ori r5,r5,HID0_BTIC
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sync
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mtspr SPRN_HID0,r5
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isync
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sync
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1:
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/* Return */
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mtmsr r7
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blr
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_GLOBAL(low_choose_7447a_dfs)
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/* Clear MSR:EE */
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mfmsr r7
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rlwinm r0,r7,0,17,15
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mtmsr r0
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/* Calc new HID1 value */
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mfspr r4,SPRN_HID1
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insrwi r4,r3,1,9 /* insert parameter into bit 9 */
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sync
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mtspr SPRN_HID1,r4
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sync
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isync
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/* Return */
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mtmsr r7
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blr
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#endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_PPC_BOOK3S_32 */
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/*
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* complement mask on the msr then "or" some values on.
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* _nmask_and_or_msr(nmask, value_to_or)
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*/
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_GLOBAL(_nmask_and_or_msr)
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mfmsr r0 /* Get current msr */
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andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
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or r0,r0,r4 /* Or on the bits in r4 (second parm) */
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SYNC /* Some chip revs have problems here... */
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mtmsr r0 /* Update machine state */
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isync
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blr /* Done */
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#ifdef CONFIG_40x
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/*
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* Do an IO access in real mode
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*/
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_GLOBAL(real_readb)
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mfmsr r7
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rlwinm r0,r7,0,~MSR_DR
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sync
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mtmsr r0
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sync
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isync
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lbz r3,0(r3)
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sync
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mtmsr r7
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sync
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isync
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blr
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/*
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* Do an IO access in real mode
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*/
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_GLOBAL(real_writeb)
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mfmsr r7
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rlwinm r0,r7,0,~MSR_DR
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sync
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mtmsr r0
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sync
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isync
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stb r3,0(r4)
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sync
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mtmsr r7
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sync
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isync
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blr
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#endif /* CONFIG_40x */
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/*
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* Flush instruction cache.
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* This is a no-op on the 601.
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*/
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#ifndef CONFIG_PPC_8xx
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_GLOBAL(flush_instruction_cache)
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#if defined(CONFIG_4xx)
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#ifdef CONFIG_403GCX
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li r3, 512
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mtctr r3
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lis r4, KERNELBASE@h
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1: iccci 0, r4
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addi r4, r4, 16
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bdnz 1b
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#else
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lis r3, KERNELBASE@h
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iccci 0,r3
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#endif
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#elif defined(CONFIG_FSL_BOOKE)
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#ifdef CONFIG_E200
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mfspr r3,SPRN_L1CSR0
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ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
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/* msync; isync recommended here */
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mtspr SPRN_L1CSR0,r3
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isync
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blr
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#endif
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mfspr r3,SPRN_L1CSR1
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ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
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mtspr SPRN_L1CSR1,r3
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#elif defined(CONFIG_PPC_BOOK3S_601)
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blr /* for 601, do nothing */
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#else
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/* 603/604 processor - use invalidate-all bit in HID0 */
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mfspr r3,SPRN_HID0
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ori r3,r3,HID0_ICFI
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mtspr SPRN_HID0,r3
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#endif /* CONFIG_4xx */
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isync
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blr
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EXPORT_SYMBOL(flush_instruction_cache)
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#endif /* CONFIG_PPC_8xx */
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/*
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* Copy a whole page. We use the dcbz instruction on the destination
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* to reduce memory traffic (it eliminates the unnecessary reads of
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* the destination into cache). This requires that the destination
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* is cacheable.
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*/
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#define COPY_16_BYTES \
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lwz r6,4(r4); \
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lwz r7,8(r4); \
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lwz r8,12(r4); \
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lwzu r9,16(r4); \
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stw r6,4(r3); \
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stw r7,8(r3); \
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stw r8,12(r3); \
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stwu r9,16(r3)
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_GLOBAL(copy_page)
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rlwinm r5, r3, 0, L1_CACHE_BYTES - 1
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addi r3,r3,-4
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0: twnei r5, 0 /* WARN if r3 is not cache aligned */
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EMIT_BUG_ENTRY 0b,__FILE__,__LINE__, BUGFLAG_WARNING
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addi r4,r4,-4
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li r5,4
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#if MAX_COPY_PREFETCH > 1
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li r0,MAX_COPY_PREFETCH
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li r11,4
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mtctr r0
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11: dcbt r11,r4
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addi r11,r11,L1_CACHE_BYTES
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bdnz 11b
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#else /* MAX_COPY_PREFETCH == 1 */
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dcbt r5,r4
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li r11,L1_CACHE_BYTES+4
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#endif /* MAX_COPY_PREFETCH */
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li r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH
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crclr 4*cr0+eq
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2:
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mtctr r0
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1:
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dcbt r11,r4
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dcbz r5,r3
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COPY_16_BYTES
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#if L1_CACHE_BYTES >= 32
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COPY_16_BYTES
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#if L1_CACHE_BYTES >= 64
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COPY_16_BYTES
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COPY_16_BYTES
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#if L1_CACHE_BYTES >= 128
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COPY_16_BYTES
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COPY_16_BYTES
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COPY_16_BYTES
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COPY_16_BYTES
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#endif
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#endif
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#endif
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bdnz 1b
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beqlr
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crnot 4*cr0+eq,4*cr0+eq
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li r0,MAX_COPY_PREFETCH
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li r11,4
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b 2b
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EXPORT_SYMBOL(copy_page)
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/*
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* Extended precision shifts.
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*
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* Updated to be valid for shift counts from 0 to 63 inclusive.
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* -- Gabriel
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*
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* R3/R4 has 64 bit value
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* R5 has shift count
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* result in R3/R4
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*
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* ashrdi3: arithmetic right shift (sign propagation)
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* lshrdi3: logical right shift
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* ashldi3: left shift
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*/
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_GLOBAL(__ashrdi3)
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subfic r6,r5,32
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srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
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addi r7,r5,32 # could be xori, or addi with -32
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slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
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rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
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sraw r7,r3,r7 # t2 = MSW >> (count-32)
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or r4,r4,r6 # LSW |= t1
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slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
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sraw r3,r3,r5 # MSW = MSW >> count
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or r4,r4,r7 # LSW |= t2
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blr
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EXPORT_SYMBOL(__ashrdi3)
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_GLOBAL(__ashldi3)
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subfic r6,r5,32
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slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
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addi r7,r5,32 # could be xori, or addi with -32
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srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
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slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
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or r3,r3,r6 # MSW |= t1
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slw r4,r4,r5 # LSW = LSW << count
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or r3,r3,r7 # MSW |= t2
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blr
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EXPORT_SYMBOL(__ashldi3)
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_GLOBAL(__lshrdi3)
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subfic r6,r5,32
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srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
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addi r7,r5,32 # could be xori, or addi with -32
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slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
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srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
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or r4,r4,r6 # LSW |= t1
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srw r3,r3,r5 # MSW = MSW >> count
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or r4,r4,r7 # LSW |= t2
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blr
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EXPORT_SYMBOL(__lshrdi3)
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|
|
|
/*
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* 64-bit comparison: __cmpdi2(s64 a, s64 b)
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* Returns 0 if a < b, 1 if a == b, 2 if a > b.
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*/
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_GLOBAL(__cmpdi2)
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cmpw r3,r5
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li r3,1
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bne 1f
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cmplw r4,r6
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beqlr
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1: li r3,0
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bltlr
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li r3,2
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blr
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|
EXPORT_SYMBOL(__cmpdi2)
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|
/*
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|
* 64-bit comparison: __ucmpdi2(u64 a, u64 b)
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|
* Returns 0 if a < b, 1 if a == b, 2 if a > b.
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*/
|
|
_GLOBAL(__ucmpdi2)
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|
cmplw r3,r5
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|
li r3,1
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|
bne 1f
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|
cmplw r4,r6
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|
beqlr
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1: li r3,0
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bltlr
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li r3,2
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blr
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|
EXPORT_SYMBOL(__ucmpdi2)
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|
|
_GLOBAL(__bswapdi2)
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rotlwi r9,r4,8
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rotlwi r10,r3,8
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rlwimi r9,r4,24,0,7
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rlwimi r10,r3,24,0,7
|
|
rlwimi r9,r4,24,16,23
|
|
rlwimi r10,r3,24,16,23
|
|
mr r3,r9
|
|
mr r4,r10
|
|
blr
|
|
EXPORT_SYMBOL(__bswapdi2)
|
|
|
|
#ifdef CONFIG_SMP
|
|
_GLOBAL(start_secondary_resume)
|
|
/* Reset stack */
|
|
rlwinm r1, r1, 0, 0, 31 - THREAD_SHIFT
|
|
addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
|
|
li r3,0
|
|
stw r3,0(r1) /* Zero the stack frame pointer */
|
|
bl start_secondary
|
|
b .
|
|
#endif /* CONFIG_SMP */
|
|
|
|
/*
|
|
* This routine is just here to keep GCC happy - sigh...
|
|
*/
|
|
_GLOBAL(__main)
|
|
blr
|
|
|
|
#ifdef CONFIG_KEXEC_CORE
|
|
/*
|
|
* Must be relocatable PIC code callable as a C function.
|
|
*/
|
|
.globl relocate_new_kernel
|
|
relocate_new_kernel:
|
|
/* r3 = page_list */
|
|
/* r4 = reboot_code_buffer */
|
|
/* r5 = start_address */
|
|
|
|
#ifdef CONFIG_FSL_BOOKE
|
|
|
|
mr r29, r3
|
|
mr r30, r4
|
|
mr r31, r5
|
|
|
|
#define ENTRY_MAPPING_KEXEC_SETUP
|
|
#include "fsl_booke_entry_mapping.S"
|
|
#undef ENTRY_MAPPING_KEXEC_SETUP
|
|
|
|
mr r3, r29
|
|
mr r4, r30
|
|
mr r5, r31
|
|
|
|
li r0, 0
|
|
#elif defined(CONFIG_44x)
|
|
|
|
/* Save our parameters */
|
|
mr r29, r3
|
|
mr r30, r4
|
|
mr r31, r5
|
|
|
|
#ifdef CONFIG_PPC_47x
|
|
/* Check for 47x cores */
|
|
mfspr r3,SPRN_PVR
|
|
srwi r3,r3,16
|
|
cmplwi cr0,r3,PVR_476FPE@h
|
|
beq setup_map_47x
|
|
cmplwi cr0,r3,PVR_476@h
|
|
beq setup_map_47x
|
|
cmplwi cr0,r3,PVR_476_ISS@h
|
|
beq setup_map_47x
|
|
#endif /* CONFIG_PPC_47x */
|
|
|
|
/*
|
|
* Code for setting up 1:1 mapping for PPC440x for KEXEC
|
|
*
|
|
* We cannot switch off the MMU on PPC44x.
|
|
* So we:
|
|
* 1) Invalidate all the mappings except the one we are running from.
|
|
* 2) Create a tmp mapping for our code in the other address space(TS) and
|
|
* jump to it. Invalidate the entry we started in.
|
|
* 3) Create a 1:1 mapping for 0-2GiB in chunks of 256M in original TS.
|
|
* 4) Jump to the 1:1 mapping in original TS.
|
|
* 5) Invalidate the tmp mapping.
|
|
*
|
|
* - Based on the kexec support code for FSL BookE
|
|
*
|
|
*/
|
|
|
|
/*
|
|
* Load the PID with kernel PID (0).
|
|
* Also load our MSR_IS and TID to MMUCR for TLB search.
|
|
*/
|
|
li r3, 0
|
|
mtspr SPRN_PID, r3
|
|
mfmsr r4
|
|
andi. r4,r4,MSR_IS@l
|
|
beq wmmucr
|
|
oris r3,r3,PPC44x_MMUCR_STS@h
|
|
wmmucr:
|
|
mtspr SPRN_MMUCR,r3
|
|
sync
|
|
|
|
/*
|
|
* Invalidate all the TLB entries except the current entry
|
|
* where we are running from
|
|
*/
|
|
bl 0f /* Find our address */
|
|
0: mflr r5 /* Make it accessible */
|
|
tlbsx r23,0,r5 /* Find entry we are in */
|
|
li r4,0 /* Start at TLB entry 0 */
|
|
li r3,0 /* Set PAGEID inval value */
|
|
1: cmpw r23,r4 /* Is this our entry? */
|
|
beq skip /* If so, skip the inval */
|
|
tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */
|
|
skip:
|
|
addi r4,r4,1 /* Increment */
|
|
cmpwi r4,64 /* Are we done? */
|
|
bne 1b /* If not, repeat */
|
|
isync
|
|
|
|
/* Create a temp mapping and jump to it */
|
|
andi. r6, r23, 1 /* Find the index to use */
|
|
addi r24, r6, 1 /* r24 will contain 1 or 2 */
|
|
|
|
mfmsr r9 /* get the MSR */
|
|
rlwinm r5, r9, 27, 31, 31 /* Extract the MSR[IS] */
|
|
xori r7, r5, 1 /* Use the other address space */
|
|
|
|
/* Read the current mapping entries */
|
|
tlbre r3, r23, PPC44x_TLB_PAGEID
|
|
tlbre r4, r23, PPC44x_TLB_XLAT
|
|
tlbre r5, r23, PPC44x_TLB_ATTRIB
|
|
|
|
/* Save our current XLAT entry */
|
|
mr r25, r4
|
|
|
|
/* Extract the TLB PageSize */
|
|
li r10, 1 /* r10 will hold PageSize */
|
|
rlwinm r11, r3, 0, 24, 27 /* bits 24-27 */
|
|
|
|
/* XXX: As of now we use 256M, 4K pages */
|
|
cmpwi r11, PPC44x_TLB_256M
|
|
bne tlb_4k
|
|
rotlwi r10, r10, 28 /* r10 = 256M */
|
|
b write_out
|
|
tlb_4k:
|
|
cmpwi r11, PPC44x_TLB_4K
|
|
bne default
|
|
rotlwi r10, r10, 12 /* r10 = 4K */
|
|
b write_out
|
|
default:
|
|
rotlwi r10, r10, 10 /* r10 = 1K */
|
|
|
|
write_out:
|
|
/*
|
|
* Write out the tmp 1:1 mapping for this code in other address space
|
|
* Fixup EPN = RPN , TS=other address space
|
|
*/
|
|
insrwi r3, r7, 1, 23 /* Bit 23 is TS for PAGEID field */
|
|
|
|
/* Write out the tmp mapping entries */
|
|
tlbwe r3, r24, PPC44x_TLB_PAGEID
|
|
tlbwe r4, r24, PPC44x_TLB_XLAT
|
|
tlbwe r5, r24, PPC44x_TLB_ATTRIB
|
|
|
|
subi r11, r10, 1 /* PageOffset Mask = PageSize - 1 */
|
|
not r10, r11 /* Mask for PageNum */
|
|
|
|
/* Switch to other address space in MSR */
|
|
insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
|
|
|
|
bl 1f
|
|
1: mflr r8
|
|
addi r8, r8, (2f-1b) /* Find the target offset */
|
|
|
|
/* Jump to the tmp mapping */
|
|
mtspr SPRN_SRR0, r8
|
|
mtspr SPRN_SRR1, r9
|
|
rfi
|
|
|
|
2:
|
|
/* Invalidate the entry we were executing from */
|
|
li r3, 0
|
|
tlbwe r3, r23, PPC44x_TLB_PAGEID
|
|
|
|
/* attribute fields. rwx for SUPERVISOR mode */
|
|
li r5, 0
|
|
ori r5, r5, (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
|
|
|
|
/* Create 1:1 mapping in 256M pages */
|
|
xori r7, r7, 1 /* Revert back to Original TS */
|
|
|
|
li r8, 0 /* PageNumber */
|
|
li r6, 3 /* TLB Index, start at 3 */
|
|
|
|
next_tlb:
|
|
rotlwi r3, r8, 28 /* Create EPN (bits 0-3) */
|
|
mr r4, r3 /* RPN = EPN */
|
|
ori r3, r3, (PPC44x_TLB_VALID | PPC44x_TLB_256M) /* SIZE = 256M, Valid */
|
|
insrwi r3, r7, 1, 23 /* Set TS from r7 */
|
|
|
|
tlbwe r3, r6, PPC44x_TLB_PAGEID /* PageID field : EPN, V, SIZE */
|
|
tlbwe r4, r6, PPC44x_TLB_XLAT /* Address translation : RPN */
|
|
tlbwe r5, r6, PPC44x_TLB_ATTRIB /* Attributes */
|
|
|
|
addi r8, r8, 1 /* Increment PN */
|
|
addi r6, r6, 1 /* Increment TLB Index */
|
|
cmpwi r8, 8 /* Are we done ? */
|
|
bne next_tlb
|
|
isync
|
|
|
|
/* Jump to the new mapping 1:1 */
|
|
li r9,0
|
|
insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
|
|
|
|
bl 1f
|
|
1: mflr r8
|
|
and r8, r8, r11 /* Get our offset within page */
|
|
addi r8, r8, (2f-1b)
|
|
|
|
and r5, r25, r10 /* Get our target PageNum */
|
|
or r8, r8, r5 /* Target jump address */
|
|
|
|
mtspr SPRN_SRR0, r8
|
|
mtspr SPRN_SRR1, r9
|
|
rfi
|
|
2:
|
|
/* Invalidate the tmp entry we used */
|
|
li r3, 0
|
|
tlbwe r3, r24, PPC44x_TLB_PAGEID
|
|
sync
|
|
b ppc44x_map_done
|
|
|
|
#ifdef CONFIG_PPC_47x
|
|
|
|
/* 1:1 mapping for 47x */
|
|
|
|
setup_map_47x:
|
|
|
|
/*
|
|
* Load the kernel pid (0) to PID and also to MMUCR[TID].
|
|
* Also set the MSR IS->MMUCR STS
|
|
*/
|
|
li r3, 0
|
|
mtspr SPRN_PID, r3 /* Set PID */
|
|
mfmsr r4 /* Get MSR */
|
|
andi. r4, r4, MSR_IS@l /* TS=1? */
|
|
beq 1f /* If not, leave STS=0 */
|
|
oris r3, r3, PPC47x_MMUCR_STS@h /* Set STS=1 */
|
|
1: mtspr SPRN_MMUCR, r3 /* Put MMUCR */
|
|
sync
|
|
|
|
/* Find the entry we are running from */
|
|
bl 2f
|
|
2: mflr r23
|
|
tlbsx r23, 0, r23
|
|
tlbre r24, r23, 0 /* TLB Word 0 */
|
|
tlbre r25, r23, 1 /* TLB Word 1 */
|
|
tlbre r26, r23, 2 /* TLB Word 2 */
|
|
|
|
|
|
/*
|
|
* Invalidates all the tlb entries by writing to 256 RPNs(r4)
|
|
* of 4k page size in all 4 ways (0-3 in r3).
|
|
* This would invalidate the entire UTLB including the one we are
|
|
* running from. However the shadow TLB entries would help us
|
|
* to continue the execution, until we flush them (rfi/isync).
|
|
*/
|
|
addis r3, 0, 0x8000 /* specify the way */
|
|
addi r4, 0, 0 /* TLB Word0 = (EPN=0, VALID = 0) */
|
|
addi r5, 0, 0
|
|
b clear_utlb_entry
|
|
|
|
/* Align the loop to speed things up. from head_44x.S */
|
|
.align 6
|
|
|
|
clear_utlb_entry:
|
|
|
|
tlbwe r4, r3, 0
|
|
tlbwe r5, r3, 1
|
|
tlbwe r5, r3, 2
|
|
addis r3, r3, 0x2000 /* Increment the way */
|
|
cmpwi r3, 0
|
|
bne clear_utlb_entry
|
|
addis r3, 0, 0x8000
|
|
addis r4, r4, 0x100 /* Increment the EPN */
|
|
cmpwi r4, 0
|
|
bne clear_utlb_entry
|
|
|
|
/* Create the entries in the other address space */
|
|
mfmsr r5
|
|
rlwinm r7, r5, 27, 31, 31 /* Get the TS (Bit 26) from MSR */
|
|
xori r7, r7, 1 /* r7 = !TS */
|
|
|
|
insrwi r24, r7, 1, 21 /* Change the TS in the saved TLB word 0 */
|
|
|
|
/*
|
|
* write out the TLB entries for the tmp mapping
|
|
* Use way '0' so that we could easily invalidate it later.
|
|
*/
|
|
lis r3, 0x8000 /* Way '0' */
|
|
|
|
tlbwe r24, r3, 0
|
|
tlbwe r25, r3, 1
|
|
tlbwe r26, r3, 2
|
|
|
|
/* Update the msr to the new TS */
|
|
insrwi r5, r7, 1, 26
|
|
|
|
bl 1f
|
|
1: mflr r6
|
|
addi r6, r6, (2f-1b)
|
|
|
|
mtspr SPRN_SRR0, r6
|
|
mtspr SPRN_SRR1, r5
|
|
rfi
|
|
|
|
/*
|
|
* Now we are in the tmp address space.
|
|
* Create a 1:1 mapping for 0-2GiB in the original TS.
|
|
*/
|
|
2:
|
|
li r3, 0
|
|
li r4, 0 /* TLB Word 0 */
|
|
li r5, 0 /* TLB Word 1 */
|
|
li r6, 0
|
|
ori r6, r6, PPC47x_TLB2_S_RWX /* TLB word 2 */
|
|
|
|
li r8, 0 /* PageIndex */
|
|
|
|
xori r7, r7, 1 /* revert back to original TS */
|
|
|
|
write_utlb:
|
|
rotlwi r5, r8, 28 /* RPN = PageIndex * 256M */
|
|
/* ERPN = 0 as we don't use memory above 2G */
|
|
|
|
mr r4, r5 /* EPN = RPN */
|
|
ori r4, r4, (PPC47x_TLB0_VALID | PPC47x_TLB0_256M)
|
|
insrwi r4, r7, 1, 21 /* Insert the TS to Word 0 */
|
|
|
|
tlbwe r4, r3, 0 /* Write out the entries */
|
|
tlbwe r5, r3, 1
|
|
tlbwe r6, r3, 2
|
|
addi r8, r8, 1
|
|
cmpwi r8, 8 /* Have we completed ? */
|
|
bne write_utlb
|
|
|
|
/* make sure we complete the TLB write up */
|
|
isync
|
|
|
|
/*
|
|
* Prepare to jump to the 1:1 mapping.
|
|
* 1) Extract page size of the tmp mapping
|
|
* DSIZ = TLB_Word0[22:27]
|
|
* 2) Calculate the physical address of the address
|
|
* to jump to.
|
|
*/
|
|
rlwinm r10, r24, 0, 22, 27
|
|
|
|
cmpwi r10, PPC47x_TLB0_4K
|
|
bne 0f
|
|
li r10, 0x1000 /* r10 = 4k */
|
|
bl 1f
|
|
|
|
0:
|
|
/* Defaults to 256M */
|
|
lis r10, 0x1000
|
|
|
|
bl 1f
|
|
1: mflr r4
|
|
addi r4, r4, (2f-1b) /* virtual address of 2f */
|
|
|
|
subi r11, r10, 1 /* offsetmask = Pagesize - 1 */
|
|
not r10, r11 /* Pagemask = ~(offsetmask) */
|
|
|
|
and r5, r25, r10 /* Physical page */
|
|
and r6, r4, r11 /* offset within the current page */
|
|
|
|
or r5, r5, r6 /* Physical address for 2f */
|
|
|
|
/* Switch the TS in MSR to the original one */
|
|
mfmsr r8
|
|
insrwi r8, r7, 1, 26
|
|
|
|
mtspr SPRN_SRR1, r8
|
|
mtspr SPRN_SRR0, r5
|
|
rfi
|
|
|
|
2:
|
|
/* Invalidate the tmp mapping */
|
|
lis r3, 0x8000 /* Way '0' */
|
|
|
|
clrrwi r24, r24, 12 /* Clear the valid bit */
|
|
tlbwe r24, r3, 0
|
|
tlbwe r25, r3, 1
|
|
tlbwe r26, r3, 2
|
|
|
|
/* Make sure we complete the TLB write and flush the shadow TLB */
|
|
isync
|
|
|
|
#endif
|
|
|
|
ppc44x_map_done:
|
|
|
|
|
|
/* Restore the parameters */
|
|
mr r3, r29
|
|
mr r4, r30
|
|
mr r5, r31
|
|
|
|
li r0, 0
|
|
#else
|
|
li r0, 0
|
|
|
|
/*
|
|
* Set Machine Status Register to a known status,
|
|
* switch the MMU off and jump to 1: in a single step.
|
|
*/
|
|
|
|
mr r8, r0
|
|
ori r8, r8, MSR_RI|MSR_ME
|
|
mtspr SPRN_SRR1, r8
|
|
addi r8, r4, 1f - relocate_new_kernel
|
|
mtspr SPRN_SRR0, r8
|
|
sync
|
|
rfi
|
|
|
|
1:
|
|
#endif
|
|
/* from this point address translation is turned off */
|
|
/* and interrupts are disabled */
|
|
|
|
/* set a new stack at the bottom of our page... */
|
|
/* (not really needed now) */
|
|
addi r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */
|
|
stw r0, 0(r1)
|
|
|
|
/* Do the copies */
|
|
li r6, 0 /* checksum */
|
|
mr r0, r3
|
|
b 1f
|
|
|
|
0: /* top, read another word for the indirection page */
|
|
lwzu r0, 4(r3)
|
|
|
|
1:
|
|
/* is it a destination page? (r8) */
|
|
rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
|
|
beq 2f
|
|
|
|
rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */
|
|
b 0b
|
|
|
|
2: /* is it an indirection page? (r3) */
|
|
rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
|
|
beq 2f
|
|
|
|
rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */
|
|
subi r3, r3, 4
|
|
b 0b
|
|
|
|
2: /* are we done? */
|
|
rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
|
|
beq 2f
|
|
b 3f
|
|
|
|
2: /* is it a source page? (r9) */
|
|
rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
|
|
beq 0b
|
|
|
|
rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */
|
|
|
|
li r7, PAGE_SIZE / 4
|
|
mtctr r7
|
|
subi r9, r9, 4
|
|
subi r8, r8, 4
|
|
9:
|
|
lwzu r0, 4(r9) /* do the copy */
|
|
xor r6, r6, r0
|
|
stwu r0, 4(r8)
|
|
dcbst 0, r8
|
|
sync
|
|
icbi 0, r8
|
|
bdnz 9b
|
|
|
|
addi r9, r9, 4
|
|
addi r8, r8, 4
|
|
b 0b
|
|
|
|
3:
|
|
|
|
/* To be certain of avoiding problems with self-modifying code
|
|
* execute a serializing instruction here.
|
|
*/
|
|
isync
|
|
sync
|
|
|
|
mfspr r3, SPRN_PIR /* current core we are running on */
|
|
mr r4, r5 /* load physical address of chunk called */
|
|
|
|
/* jump to the entry point, usually the setup routine */
|
|
mtlr r5
|
|
blrl
|
|
|
|
1: b 1b
|
|
|
|
relocate_new_kernel_end:
|
|
|
|
.globl relocate_new_kernel_size
|
|
relocate_new_kernel_size:
|
|
.long relocate_new_kernel_end - relocate_new_kernel
|
|
#endif
|