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2874c5fd28
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
93 lines
2.0 KiB
ArmAsm
93 lines
2.0 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved.
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* Dave Liu <daveliu@freescale.com>
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* copy from idle_6xx.S and modify for e500 based processor,
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* implement the power_save function in idle.
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*/
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#include <linux/threads.h>
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/cputable.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/feature-fixups.h>
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.text
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_GLOBAL(e500_idle)
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lwz r4,TI_LOCAL_FLAGS(r2) /* set napping bit */
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ori r4,r4,_TLF_NAPPING /* so when we take an exception */
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stw r4,TI_LOCAL_FLAGS(r2) /* it will return to our caller */
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#ifdef CONFIG_PPC_E500MC
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wrteei 1
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1: wait
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/*
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* Guard against spurious wakeups (e.g. from a hypervisor) --
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* any real interrupt will cause us to return to LR due to
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* _TLF_NAPPING.
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*/
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b 1b
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#else
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/* Check if we can nap or doze, put HID0 mask in r3 */
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lis r3,0
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BEGIN_FTR_SECTION
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lis r3,HID0_DOZE@h
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END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE)
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BEGIN_FTR_SECTION
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/* Now check if user enabled NAP mode */
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lis r4,powersave_nap@ha
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lwz r4,powersave_nap@l(r4)
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cmpwi 0,r4,0
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beq 1f
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stwu r1,-16(r1)
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mflr r0
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stw r0,20(r1)
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bl flush_dcache_L1
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lwz r0,20(r1)
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addi r1,r1,16
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mtlr r0
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lis r3,HID0_NAP@h
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END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
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1:
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/* Go to NAP or DOZE now */
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mfspr r4,SPRN_HID0
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rlwinm r4,r4,0,~(HID0_DOZE|HID0_NAP|HID0_SLEEP)
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or r4,r4,r3
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isync
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mtspr SPRN_HID0,r4
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isync
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mfmsr r7
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oris r7,r7,MSR_WE@h
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ori r7,r7,MSR_EE
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msync
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mtmsr r7
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isync
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2: b 2b
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#endif /* !E500MC */
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/*
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* Return from NAP/DOZE mode, restore some CPU specific registers,
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* r2 containing physical address of current.
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* r11 points to the exception frame (physical address).
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* We have to preserve r10.
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*/
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_GLOBAL(power_save_ppc32_restore)
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lwz r9,_LINK(r11) /* interrupted in e500_idle */
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stw r9,_NIP(r11) /* make it do a blr */
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#ifdef CONFIG_SMP
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lwz r11,TASK_CPU(r2) /* get cpu number * 4 */
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slwi r11,r11,2
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#else
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li r11,0
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#endif
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b transfer_to_handler_cont
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