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Based on 1 normalized pattern(s): this program is free software you can distribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 32 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528170026.531157061@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
251 lines
6.1 KiB
C
251 lines
6.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
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* Copyright (C) 2008 Dmitri Vorobiev
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*/
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#include <linux/cpu.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/of_fdt.h>
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#include <linux/pci.h>
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#include <linux/screen_info.h>
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#include <linux/time.h>
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#include <asm/dma-coherence.h>
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#include <asm/fw/fw.h>
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#include <asm/mach-malta/malta-dtshim.h>
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#include <asm/mips-cps.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/mips-boards/malta.h>
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#include <asm/mips-boards/maltaint.h>
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#include <asm/dma.h>
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#include <asm/prom.h>
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#include <asm/traps.h>
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#ifdef CONFIG_VT
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#include <linux/console.h>
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#endif
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#define ROCIT_CONFIG_GEN0 0x1f403000
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#define ROCIT_CONFIG_GEN0_PCI_IOCU BIT(7)
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static struct resource standard_io_resources[] = {
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{
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.name = "dma1",
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.start = 0x00,
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.end = 0x1f,
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.flags = IORESOURCE_IO | IORESOURCE_BUSY
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},
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{
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.name = "timer",
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.start = 0x40,
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.end = 0x5f,
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.flags = IORESOURCE_IO | IORESOURCE_BUSY
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},
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{
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.name = "keyboard",
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.start = 0x60,
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.end = 0x6f,
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.flags = IORESOURCE_IO | IORESOURCE_BUSY
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},
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{
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.name = "dma page reg",
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.start = 0x80,
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.end = 0x8f,
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.flags = IORESOURCE_IO | IORESOURCE_BUSY
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},
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{
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.name = "dma2",
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.start = 0xc0,
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.end = 0xdf,
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.flags = IORESOURCE_IO | IORESOURCE_BUSY
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},
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};
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const char *get_system_type(void)
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{
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return "MIPS Malta";
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}
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#ifdef CONFIG_BLK_DEV_FD
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static void __init fd_activate(void)
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{
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/*
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* Activate Floppy Controller in the SMSC FDC37M817 Super I/O
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* Controller.
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* Done by YAMON 2.00 onwards
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*/
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/* Entering config state. */
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SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
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/* Activate floppy controller. */
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SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
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SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
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SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
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SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
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/* Exit config state. */
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SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
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}
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#endif
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static int __init plat_enable_iocoherency(void)
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{
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int supported = 0;
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u32 cfg;
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if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
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if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
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BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
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pr_info("Enabled Bonito CPU coherency\n");
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supported = 1;
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}
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if (strstr(fw_getcmdline(), "iobcuncached")) {
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BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
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BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
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~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
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BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
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pr_info("Disabled Bonito IOBC coherency\n");
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} else {
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BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
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BONITO_PCIMEMBASECFG |=
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(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
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BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
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pr_info("Enabled Bonito IOBC coherency\n");
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}
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} else if (mips_cps_numiocu(0) != 0) {
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/* Nothing special needs to be done to enable coherency */
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pr_info("CMP IOCU detected\n");
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cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0));
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if (!(cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)) {
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pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
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return 0;
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}
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supported = 1;
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}
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hw_coherentio = supported;
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return supported;
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}
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static void __init plat_setup_iocoherency(void)
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{
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if (plat_enable_iocoherency()) {
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if (coherentio == IO_COHERENCE_DISABLED)
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pr_info("Hardware DMA cache coherency disabled\n");
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else
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pr_info("Hardware DMA cache coherency enabled\n");
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} else {
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if (coherentio == IO_COHERENCE_ENABLED)
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pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
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else
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pr_info("Software DMA cache coherency enabled\n");
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}
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}
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static void __init pci_clock_check(void)
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{
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unsigned int __iomem *jmpr_p =
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(unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
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int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
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static const int pciclocks[] __initconst = {
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33, 20, 25, 30, 12, 16, 37, 10
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};
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int pciclock = pciclocks[jmpr];
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char *optptr, *argptr = fw_getcmdline();
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/*
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* If user passed a pci_clock= option, don't tack on another one
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*/
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optptr = strstr(argptr, "pci_clock=");
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if (optptr && (optptr == argptr || optptr[-1] == ' '))
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return;
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if (pciclock != 33) {
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pr_warn("WARNING: PCI clock is %dMHz, setting pci_clock\n",
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pciclock);
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argptr += strlen(argptr);
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sprintf(argptr, " pci_clock=%d", pciclock);
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if (pciclock < 20 || pciclock > 66)
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pr_warn("WARNING: IDE timing calculations will be "
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"incorrect\n");
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}
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}
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#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
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static void __init screen_info_setup(void)
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{
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screen_info = (struct screen_info) {
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.orig_x = 0,
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.orig_y = 25,
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.ext_mem_k = 0,
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.orig_video_page = 0,
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.orig_video_mode = 0,
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.orig_video_cols = 80,
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.unused2 = 0,
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.orig_video_ega_bx = 0,
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.unused3 = 0,
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.orig_video_lines = 25,
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.orig_video_isVGA = VIDEO_TYPE_VGAC,
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.orig_video_points = 16
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};
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}
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#endif
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static void __init bonito_quirks_setup(void)
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{
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char *argptr;
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argptr = fw_getcmdline();
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if (strstr(argptr, "debug")) {
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BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
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pr_info("Enabled Bonito debug mode\n");
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} else
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BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
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}
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void __init *plat_get_fdt(void)
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{
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return (void *)__dtb_start;
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}
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void __init plat_mem_setup(void)
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{
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unsigned int i;
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void *fdt = plat_get_fdt();
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fdt = malta_dt_shim(fdt);
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__dt_setup_arch(fdt);
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if (IS_ENABLED(CONFIG_EVA))
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/* EVA has already been configured in mach-malta/kernel-init.h */
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pr_info("Enhanced Virtual Addressing (EVA) activated\n");
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mips_pcibios_init();
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/* Request I/O space for devices used on the Malta board. */
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for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
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request_resource(&ioport_resource, standard_io_resources+i);
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/*
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* Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
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*/
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enable_dma(4);
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if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)
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bonito_quirks_setup();
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plat_setup_iocoherency();
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pci_clock_check();
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#ifdef CONFIG_BLK_DEV_FD
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fd_activate();
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#endif
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#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
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screen_info_setup();
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#endif
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}
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