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2874c5fd28
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
136 lines
3.7 KiB
C
136 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Bus error event handling code for 5000-series systems equipped
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* with parity error detection logic, i.e. DECstation/DECsystem
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* 5000/120, /125, /133 (KN02-BA), 5000/150 (KN04-BA) and Personal
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* DECstation/DECsystem 5000/20, /25, /33 (KN02-CA), 5000/50
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* (KN04-CA) systems.
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*
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* Copyright (c) 2005 Maciej W. Rozycki
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <asm/addrspace.h>
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#include <asm/cpu-type.h>
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#include <asm/irq_regs.h>
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#include <asm/ptrace.h>
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#include <asm/traps.h>
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#include <asm/dec/kn02ca.h>
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#include <asm/dec/kn02xa.h>
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#include <asm/dec/kn05.h>
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static inline void dec_kn02xa_be_ack(void)
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{
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volatile u32 *mer = (void *)CKSEG1ADDR(KN02XA_MER);
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volatile u32 *mem_intr = (void *)CKSEG1ADDR(KN02XA_MEM_INTR);
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*mer = KN02CA_MER_INTR; /* Clear errors; keep the ARC IRQ. */
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*mem_intr = 0; /* Any write clears the bus IRQ. */
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iob();
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}
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static int dec_kn02xa_be_backend(struct pt_regs *regs, int is_fixup,
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int invoker)
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{
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volatile u32 *kn02xa_mer = (void *)CKSEG1ADDR(KN02XA_MER);
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volatile u32 *kn02xa_ear = (void *)CKSEG1ADDR(KN02XA_EAR);
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static const char excstr[] = "exception";
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static const char intstr[] = "interrupt";
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static const char cpustr[] = "CPU";
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static const char mreadstr[] = "memory read";
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static const char readstr[] = "read";
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static const char writestr[] = "write";
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static const char timestr[] = "timeout";
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static const char paritystr[] = "parity error";
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static const char lanestat[][4] = { " OK", "BAD" };
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const char *kind, *agent, *cycle, *event;
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unsigned long address;
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u32 mer = *kn02xa_mer;
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u32 ear = *kn02xa_ear;
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int action = MIPS_BE_FATAL;
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/* Ack ASAP, so that any subsequent errors get caught. */
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dec_kn02xa_be_ack();
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kind = invoker ? intstr : excstr;
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/* No DMA errors? */
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agent = cpustr;
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address = ear & KN02XA_EAR_ADDRESS;
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/* Low 256MB is decoded as memory, high -- as TC. */
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if (address < 0x10000000) {
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cycle = mreadstr;
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event = paritystr;
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} else {
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cycle = invoker ? writestr : readstr;
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event = timestr;
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}
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if (is_fixup)
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action = MIPS_BE_FIXUP;
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if (action != MIPS_BE_FIXUP)
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printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
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kind, agent, cycle, event, address);
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if (action != MIPS_BE_FIXUP && address < 0x10000000)
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printk(KERN_ALERT " Byte lane status %#3x -- "
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"#3: %s, #2: %s, #1: %s, #0: %s\n",
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(mer & KN02XA_MER_BYTERR) >> 8,
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lanestat[(mer & KN02XA_MER_BYTERR_3) != 0],
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lanestat[(mer & KN02XA_MER_BYTERR_2) != 0],
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lanestat[(mer & KN02XA_MER_BYTERR_1) != 0],
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lanestat[(mer & KN02XA_MER_BYTERR_0) != 0]);
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return action;
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}
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int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup)
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{
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return dec_kn02xa_be_backend(regs, is_fixup, 0);
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}
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irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id)
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{
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struct pt_regs *regs = get_irq_regs();
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int action = dec_kn02xa_be_backend(regs, 0, 1);
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if (action == MIPS_BE_DISCARD)
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return IRQ_HANDLED;
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/*
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* FIXME: Find the affected processes and kill them, otherwise
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* we must die.
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*
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* The interrupt is asynchronously delivered thus EPC and RA
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* may be irrelevant, but are printed for a reference.
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*/
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printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n",
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regs->cp0_epc, regs->regs[31]);
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die("Unrecoverable bus error", regs);
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}
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void __init dec_kn02xa_be_init(void)
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{
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volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
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/* For KN04 we need to make sure EE (?) is enabled in the MB. */
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if (current_cpu_type() == CPU_R4000SC)
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*mbcs |= KN4K_MB_CSR_EE;
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fast_iob();
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/* Clear any leftover errors from the firmware. */
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dec_kn02xa_be_ack();
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}
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