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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
101 lines
2.4 KiB
C
101 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* pci.c -- basic PCI support code
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*
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* (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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/*
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* From arch/i386/kernel/pci-i386.c:
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*
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* We need to avoid collisions with `mirrored' VGA ports
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* and other strange ISA hardware, so we always want the
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* addresses to be allocated in the 0x000-0x0ff region
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* modulo 0x400.
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*
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* Why? Because some silly external IO cards only decode
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* the low 10 bits of the IO address. The 0x00-0xff region
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* is reserved for motherboard devices that decode all 16
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* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
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* but we want to try to avoid allocating at 0x2900-0x2bff
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* which might be mirrored at 0x0100-0x03ff..
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*/
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resource_size_t pcibios_align_resource(void *data, const struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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resource_size_t start = res->start;
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if ((res->flags & IORESOURCE_IO) && (start & 0x300))
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start = (start + 0x3ff) & ~0x3ff;
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start = (start + align - 1) & ~(align - 1);
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return start;
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}
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/*
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* This is taken from the ARM code for this.
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*/
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int pcibios_enable_device(struct pci_dev *dev, int mask)
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{
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struct resource *r;
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u16 cmd, newcmd;
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int idx;
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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newcmd = cmd;
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for (idx = 0; idx < 6; idx++) {
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/* Only set up the requested stuff */
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if (!(mask & (1 << idx)))
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continue;
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r = dev->resource + idx;
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if (!r->start && r->end) {
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pr_err("PCI: Device %s not available because of resource collisions\n",
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pci_name(dev));
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return -EINVAL;
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}
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if (r->flags & IORESOURCE_IO)
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newcmd |= PCI_COMMAND_IO;
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if (r->flags & IORESOURCE_MEM)
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newcmd |= PCI_COMMAND_MEMORY;
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}
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/*
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* Bridges (eg, cardbus bridges) need to be fully enabled
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*/
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if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
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newcmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
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if (newcmd != cmd) {
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pr_info("PCI: enabling device %s (0x%04x -> 0x%04x)\n",
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pci_name(dev), cmd, newcmd);
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pci_write_config_word(dev, PCI_COMMAND, newcmd);
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}
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return 0;
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}
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void pcibios_fixup_bus(struct pci_bus *bus)
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{
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struct pci_dev *dev;
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list_for_each_entry(dev, &bus->devices, bus_list) {
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 32);
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}
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}
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char *pcibios_setup(char *str)
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{
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return str;
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}
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