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https://github.com/brain-hackers/linux-brain.git
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ae76f635d4
DMA_FROM_DEVICE only need to read dma data of memory into CPU cache, so there is no need to clear cache before. Also clear + inv for DMA_FROM_DEVICE won't cause problem, because the memory range for dma won't be touched by software during dma working. Changes for V2: - Remove clr cache and ignore the DMA_TO_DEVICE in _for_cpu. - Change inv to wbinv cache with DMA_FROM_DEVICE in _for_device. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Arnd Bergmann <arnd@arndb.de>
89 lines
2.1 KiB
C
89 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#include <linux/spinlock.h>
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#include <linux/smp.h>
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#include <asm/cache.h>
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#include <asm/barrier.h>
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inline void dcache_wb_line(unsigned long start)
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{
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asm volatile("dcache.cval1 %0\n"::"r"(start):"memory");
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sync_is();
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}
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void icache_inv_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("icache.iva %0\n"::"r"(i):"memory");
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sync_is();
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}
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void icache_inv_all(void)
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{
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asm volatile("icache.ialls\n":::"memory");
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sync_is();
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}
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void dcache_wb_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("dcache.cval1 %0\n"::"r"(i):"memory");
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sync_is();
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}
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void dcache_inv_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("dcache.civa %0\n"::"r"(i):"memory");
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sync_is();
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}
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void cache_wbinv_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("dcache.cval1 %0\n"::"r"(i):"memory");
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sync_is();
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i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("icache.iva %0\n"::"r"(i):"memory");
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sync_is();
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}
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EXPORT_SYMBOL(cache_wbinv_range);
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void dma_wbinv_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("dcache.civa %0\n"::"r"(i):"memory");
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sync_is();
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}
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void dma_inv_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("dcache.iva %0\n"::"r"(i):"memory");
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sync_is();
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}
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void dma_wb_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("dcache.cva %0\n"::"r"(i):"memory");
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sync_is();
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}
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