Liu Yibin f3f23f4c64 csky: Fixup msa highest 3 bits mask ... [ Upstream commit 165f2d2858013253042809df082b8df7e34e86d7 ] Just as comment mentioned, the msa format: cr<30/31, 15> MSA register format: 31 - 29 | 28 - 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 BA Reserved SH WA B SO SEC C D V So we should shift 29 bits not 28 bits for mask Signed-off-by: Liu Yibin <jiulong@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Sasha Levin <sashal@kernel.org>		2020-06-03 08:21:13 +02:00
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cacheflush.h	csky: Fixup 610 vipt cache flush mechanism	2019-08-22 10:44:24 +08:00
ckmmu.h	csky: Use generic asid algorithm to implement switch_mm	2019-07-19 14:21:36 +08:00
elf.h	csky: ELF and module probe	2018-10-26 00:54:23 +08:00
entry.h	csky: Fixup msa highest 3 bits mask	2020-06-03 08:21:13 +02:00
page.h	csky: Fixup arch_get_unmapped_area() implementation	2019-08-20 16:09:37 +08:00
pgtable-bits.h	csky: fixup abiv2 mmap(... O_SYNC) failed.	2018-12-31 10:56:45 +08:00
reg_ops.h	csky: Misc headers	2018-10-26 00:54:26 +08:00
regdef.h	csky: Add perf_arch_fetch_caller_regs support	2019-04-22 13:44:57 +08:00
string.h	csky: Fixup abiv1 memset error	2019-07-19 14:21:36 +08:00
switch_context.h	csky: fixup save hi,lo,dspcr regs in switch_stack.	2018-12-31 22:57:27 +08:00
vdso.h	csky: VDSO and rt_sigreturn	2018-10-26 00:54:22 +08:00