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Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
110 lines
2.9 KiB
C
110 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* linux/arch/arm/plat-versatile/platsmp.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This code is specific to the hardware found on ARM Realview and
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* Versatile Express platforms where the CPUs are unable to be individually
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* woken, and where there is no way to hot-unplug CPUs. Real platforms
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* should not copy this code.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#include <plat/platsmp.h>
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/*
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* versatile_cpu_release controls the release of CPUs from the holding
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* pen in headsmp.S, which exists because we are not always able to
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* control the release of individual CPUs from the board firmware.
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* Production platforms do not need this.
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*/
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volatile int versatile_cpu_release = -1;
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/*
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* Write versatile_cpu_release in a way that is guaranteed to be visible to
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* all observers, irrespective of whether they're taking part in coherency
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* or not. This is necessary for the hotplug code to work reliably.
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*/
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static void versatile_write_cpu_release(int val)
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{
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versatile_cpu_release = val;
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smp_wmb();
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sync_cache_w(&versatile_cpu_release);
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}
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/*
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* versatile_lock exists to avoid running the loops_per_jiffy delay loop
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* calibrations on the secondary CPU while the requesting CPU is using
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* the limited-bandwidth bus - which affects the calibration value.
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* Production platforms do not need this.
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*/
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static DEFINE_RAW_SPINLOCK(versatile_lock);
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void versatile_secondary_init(unsigned int cpu)
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{
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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versatile_write_cpu_release(-1);
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/*
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* Synchronise with the boot thread.
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*/
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raw_spin_lock(&versatile_lock);
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raw_spin_unlock(&versatile_lock);
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}
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int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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/*
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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raw_spin_lock(&versatile_lock);
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/*
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* This is really belt and braces; we hold unintended secondary
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* CPUs in the holding pen until we're ready for them. However,
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* since we haven't sent them a soft interrupt, they shouldn't
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* be there.
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*/
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versatile_write_cpu_release(cpu_logical_map(cpu));
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/*
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* Send the secondary CPU a soft interrupt, thereby causing
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* the boot monitor to read the system wide flags register,
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* and branch to the address found there.
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*/
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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smp_rmb();
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if (versatile_cpu_release == -1)
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break;
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udelay(10);
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}
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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raw_spin_unlock(&versatile_lock);
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return versatile_cpu_release != -1 ? -ENOSYS : 0;
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}
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