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3584be9ec3
In a multiplatform configuration, enabling DEBUG_LL breaks booting on all platforms with incompatible settings. In case of the Marvell platforms of the Orion/MVEBU family, the physical addresses are all the same, we just map them at different virtual addresses, which makes it impossible to run a kernel with DEBUG_LL enabled on a combination of the merged mvebu and the legacy boardfile based platforms. This is easily solved by using the same virtual address everywhere. I picked the address that is already used by mach-mvebu for UART0: 0xfec12000. All these platforms have a 1MB region with their internal registers, almost always at physical address 0xf1000000, so I'm updating the iotable for that entry. In case of mach-dove, this is slightly trickier, as the existing mapping is 8MB and a second 8MB mapping is already at the 0xfec00000 address. I have verified from the datasheet that the last 7MB of the physical mapping are "reserved" and nothing in Linux tries to use it either. I'm putting this 1MB mapping at the same address as the others, and the second 8MB register area immediately before that. Link: https://lore.kernel.org/r/20190731195713.3150463-14-arnd@arndb.de Link: https://lore.kernel.org/linux-arm-kernel/87si3eb1z8.fsf@free-electrons.com/ Signed-off-by: Arnd Bergmann <arnd@arndb.de>
147 lines
5.6 KiB
C
147 lines
5.6 KiB
C
/*
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* Generic definitions of Orion SoC flavors:
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* Orion-1, Orion-VoIP, Orion-NAS, Orion-2, and Orion-1-90.
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*
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_ORION5X_H
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#define __ASM_ARCH_ORION5X_H
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#include "irqs.h"
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/*****************************************************************************
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* Orion Address Maps
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*
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* phys
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* e0000000 PCIe MEM space
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* e8000000 PCI MEM space
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* f0000000 PCIe WA space (Orion-1/Orion-NAS only)
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* f1000000 on-chip peripheral registers
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* f2000000 PCIe I/O space
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* f2100000 PCI I/O space
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* f2200000 SRAM dedicated for the crypto unit
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* f4000000 device bus mappings (boot)
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* fa000000 device bus mappings (cs0)
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* fa800000 device bus mappings (cs2)
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* fc000000 device bus mappings (cs0/cs1)
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*
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* virt phys size
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* fec00000 f1000000 1M on-chip peripheral registers
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* fee00000 f2000000 64K PCIe I/O space
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* fee10000 f2100000 64K PCI I/O space
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* fd000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only)
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****************************************************************************/
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#define ORION5X_REGS_PHYS_BASE 0xf1000000
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#define ORION5X_REGS_VIRT_BASE IOMEM(0xfec00000)
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#define ORION5X_REGS_SIZE SZ_1M
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#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000
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#define ORION5X_PCIE_IO_BUS_BASE 0x00000000
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#define ORION5X_PCIE_IO_SIZE SZ_64K
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#define ORION5X_PCI_IO_PHYS_BASE 0xf2100000
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#define ORION5X_PCI_IO_BUS_BASE 0x00010000
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#define ORION5X_PCI_IO_SIZE SZ_64K
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#define ORION5X_SRAM_PHYS_BASE (0xf2200000)
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#define ORION5X_SRAM_SIZE SZ_8K
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/* Relevant only for Orion-1/Orion-NAS */
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#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
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#define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
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#define ORION5X_PCIE_WA_SIZE SZ_16M
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#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000
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#define ORION5X_PCIE_MEM_SIZE SZ_128M
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#define ORION5X_PCI_MEM_PHYS_BASE 0xe8000000
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#define ORION5X_PCI_MEM_SIZE SZ_128M
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/*******************************************************************************
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* Orion Registers Map
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******************************************************************************/
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#define ORION5X_DDR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x00000)
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#define ORION5X_DDR_WINS_BASE (ORION5X_DDR_PHYS_BASE + 0x1500)
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#define ORION5X_DDR_WINS_SZ (0x10)
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#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x00000)
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#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x10000)
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#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x10000)
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#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE + (x))
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#define GPIO_VIRT_BASE ORION5X_DEV_BUS_REG(0x0100)
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#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x0600)
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#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x1000)
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#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2000)
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#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2000)
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#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2100)
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#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2100)
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#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x20000)
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#define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x20000)
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#define ORION5X_BRIDGE_WINS_BASE (ORION5X_BRIDGE_PHYS_BASE)
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#define ORION5X_BRIDGE_WINS_SZ (0x80)
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#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x30000)
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#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x40000)
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#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x50000)
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#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x50000)
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#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x60900)
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#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x60900)
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#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x70000)
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#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x70000)
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#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x80000)
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#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x80000)
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#define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x90000)
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#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0xa0000)
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#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0xa0000)
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/*******************************************************************************
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* Device Bus Registers
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******************************************************************************/
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#define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000)
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#define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004)
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#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050)
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#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008)
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#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010)
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#define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c)
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#define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460)
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#define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464)
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#define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c)
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#define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0)
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#define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0)
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#define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4)
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/*******************************************************************************
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* Supported Devices & Revisions
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******************************************************************************/
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/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
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#define MV88F5181_DEV_ID 0x5181
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#define MV88F5181_REV_B1 3
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#define MV88F5181L_REV_A0 8
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#define MV88F5181L_REV_A1 9
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/* Orion-NAS (88F5182) */
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#define MV88F5182_DEV_ID 0x5182
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#define MV88F5182_REV_A2 2
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/* Orion-2 (88F5281) */
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#define MV88F5281_DEV_ID 0x5281
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#define MV88F5281_REV_D0 4
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#define MV88F5281_REV_D1 5
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#define MV88F5281_REV_D2 6
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/* Orion-1-90 (88F6183) */
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#define MV88F6183_DEV_ID 0x6183
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#define MV88F6183_REV_B0 3
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#endif
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