mirror of
https://github.com/brain-hackers/linux-brain.git
synced 2024-06-09 15:26:21 +09:00
7c607944bc
The CNTVOFF register from arch timer is uninitialized. It should be done by the bootloader but it is currently not the case, even for boot CPU because this SoC is booting in secure mode. It leads to an random offset value meaning that each CPU will have a different time, which isn't working very well. Add assembly code used for boot CPU and secondary CPU cores to make sure that the CNTVOFF register is initialized. Because this code can be used by different platforms, add this assembly file in ARM's common folder. Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
33 lines
825 B
ArmAsm
33 lines
825 B
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* Copyright (C) 2014 Renesas Electronics Corporation
|
|
*
|
|
* Initialization of CNTVOFF register from secure mode
|
|
*
|
|
*/
|
|
|
|
#include <linux/linkage.h>
|
|
#include <asm/assembler.h>
|
|
|
|
ENTRY(secure_cntvoff_init)
|
|
.arch armv7-a
|
|
/*
|
|
* CNTVOFF has to be initialized either from non-secure Hypervisor
|
|
* mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
|
|
* then it should be handled by the secure code. The CPU must implement
|
|
* the virtualization extensions.
|
|
*/
|
|
cps #MON_MODE
|
|
mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */
|
|
orr r0, r1, #1
|
|
mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */
|
|
isb
|
|
mov r0, #0
|
|
mcrr p15, 4, r0, r0, c14 /* CNTVOFF = 0 */
|
|
isb
|
|
mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */
|
|
isb
|
|
cps #SVC_MODE
|
|
ret lr
|
|
ENDPROC(secure_cntvoff_init)
|