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Krait CPUs have a handful of L2 cache controller registers that live behind a cp15 based indirection register. First you program the indirection register (l2cpselr) to point the L2 'window' register (l2cpdr) at what you want to read/write. Then you read/write the 'window' register to do what you want. The l2cpselr register is not banked per-cpu so we must lock around accesses to it to prevent other CPUs from re-pointing l2cpdr underneath us. Cc: Mark Rutland <mark.rutland@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Craig Tatlor <ctatlor97@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
21 lines
239 B
Plaintext
21 lines
239 B
Plaintext
# SPDX-License-Identifier: GPL-2.0
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config SA1111
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bool
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select DMABOUNCE if !ARCH_PXA
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config DMABOUNCE
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bool
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select ZONE_DMA
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config KRAIT_L2_ACCESSORS
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bool
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config SHARP_LOCOMO
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bool
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config SHARP_PARAM
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bool
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config SHARP_SCOOP
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bool
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