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https://github.com/brain-hackers/linux-brain.git
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d2912cb15b
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
144 lines
2.7 KiB
ArmAsm
144 lines
2.7 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
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*/
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#include <linux/linkage.h>
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#include <asm/cache.h>
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/*
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* The memset implementation below is optimized to use prefetchw and prealloc
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* instruction in case of CPU with 64B L1 data cache line (L1_CACHE_SHIFT == 6)
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* If you want to implement optimized memset for other possible L1 data cache
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* line lengths (32B and 128B) you should rewrite code carefully checking
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* we don't call any prefetchw/prealloc instruction for L1 cache lines which
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* don't belongs to memset area.
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*/
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#if L1_CACHE_SHIFT == 6
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.macro PREALLOC_INSTR reg, off
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prealloc [\reg, \off]
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.endm
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.macro PREFETCHW_INSTR reg, off
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prefetchw [\reg, \off]
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.endm
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#else
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.macro PREALLOC_INSTR reg, off
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.endm
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.macro PREFETCHW_INSTR reg, off
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.endm
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#endif
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ENTRY_CFI(memset)
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PREFETCHW_INSTR r0, 0 ; Prefetch the first write location
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mov.f 0, r2
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;;; if size is zero
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jz.d [blink]
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mov r3, r0 ; don't clobber ret val
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;;; if length < 8
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brls.d.nt r2, 8, .Lsmallchunk
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mov.f lp_count,r2
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and.f r4, r0, 0x03
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rsub lp_count, r4, 4
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lpnz @.Laligndestination
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;; LOOP BEGIN
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stb.ab r1, [r3,1]
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sub r2, r2, 1
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.Laligndestination:
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;;; Destination is aligned
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and r1, r1, 0xFF
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asl r4, r1, 8
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or r4, r4, r1
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asl r5, r4, 16
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or r5, r5, r4
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mov r4, r5
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sub3 lp_count, r2, 8
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cmp r2, 64
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bmsk.hi r2, r2, 5
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mov.ls lp_count, 0
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add3.hi r2, r2, 8
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;;; Convert len to Dwords, unfold x8
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lsr.f lp_count, lp_count, 6
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lpnz @.Lset64bytes
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;; LOOP START
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PREALLOC_INSTR r3, 64 ; alloc next line w/o fetching
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#ifdef CONFIG_ARC_HAS_LL64
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std.ab r4, [r3, 8]
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std.ab r4, [r3, 8]
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std.ab r4, [r3, 8]
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std.ab r4, [r3, 8]
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std.ab r4, [r3, 8]
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std.ab r4, [r3, 8]
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std.ab r4, [r3, 8]
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std.ab r4, [r3, 8]
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#else
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st.ab r4, [r3, 4]
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st.ab r4, [r3, 4]
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st.ab r4, [r3, 4]
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st.ab r4, [r3, 4]
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st.ab r4, [r3, 4]
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st.ab r4, [r3, 4]
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st.ab r4, [r3, 4]
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st.ab r4, [r3, 4]
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st.ab r4, [r3, 4]
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st.ab r4, [r3, 4]
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st.ab r4, [r3, 4]
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st.ab r4, [r3, 4]
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st.ab r4, [r3, 4]
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st.ab r4, [r3, 4]
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st.ab r4, [r3, 4]
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st.ab r4, [r3, 4]
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#endif
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.Lset64bytes:
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lsr.f lp_count, r2, 5 ;Last remaining max 124 bytes
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lpnz .Lset32bytes
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;; LOOP START
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#ifdef CONFIG_ARC_HAS_LL64
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std.ab r4, [r3, 8]
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std.ab r4, [r3, 8]
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std.ab r4, [r3, 8]
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std.ab r4, [r3, 8]
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#else
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st.ab r4, [r3, 4]
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st.ab r4, [r3, 4]
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st.ab r4, [r3, 4]
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st.ab r4, [r3, 4]
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st.ab r4, [r3, 4]
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st.ab r4, [r3, 4]
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st.ab r4, [r3, 4]
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st.ab r4, [r3, 4]
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#endif
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.Lset32bytes:
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and.f lp_count, r2, 0x1F ;Last remaining 31 bytes
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.Lsmallchunk:
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lpnz .Lcopy3bytes
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;; LOOP START
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stb.ab r1, [r3, 1]
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.Lcopy3bytes:
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j [blink]
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END_CFI(memset)
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ENTRY_CFI(memzero)
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; adjust bzero args to memset args
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mov r2, r1
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b.d memset ;tail call so need to tinker with blink
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mov r1, 0
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END_CFI(memzero)
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