SATA driver write to regisers in the PCIE_A power domain and
hence PCIE_A needs to be powered on even when ONLY SATA is enabled.
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Enabling use of the first SECO MU on i.MX8QM
Signed-off-by: Stephane Dion <stephane.dion_1@nxp.com>
(cherry picked from commit 2b65b323254965b1d563e0aee80e18678d631b9d)
(cherry picked from commit 5ff969719af8a80a8146fcbd856f5d28562c1081)
Split dma channel power domain from sub-domain of dma customer driver
such as Audio, LPSPI, LPUART.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: S.j. Wang <shengjiu.wang@nxp.com>
Since RPMSG switches to use LSIO's MU instead of M4's MU,
the LSIO MU's irq is inside GIC IRQ domain, NOT in intmux
irq domain, so no need to power on intmux early during system
resume.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
With current code, the index are stored in an array at their common index,
ie jr0 store at index 0, jr1 at 1, ...
It force to use buggy mechanic to compute it and is not scalable.
This patch removes the mechanic of computation of hardware register
addresses and the notion of first_jr_index.
Instead the first JR available is set to index 0 of the table and so on.
Legacy code was retrieving the index of the first jr to access registers.
With this new way, we simply always access the first jr.
This is working because after the configuration of the JR in ctl
(enable_jobrings), the driver checks that there is at least 1 JR.
Without this, we could create segfaults.
Fixes: e9688f0f05 ("MLK-15473-1: crypto: caam: Add CAAM driver support for iMX8 soc family")
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
We are currently using SC_R_LAST as a marker for imx8 power domain tree
nodes without a resource attached. This value is compiled into dtb as
part of the linux build and used by uboot.
The SC_R_LAST constant changes frequently as SCFW resources are added
(by design) and every time we need to update linux and uboot headers
together or boot can fail.
Fix this by replacing SC_R_LAST usage with a new constant SC_R_NONE
defined to be 0xFFF0.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Until now, the DSI PHY_REF clock was by default ON in SCFW, which made
this clock unusable in kernel, therefore, this clock was set as
CLK_DUMMY in DSI device nodes.
Sinnce this clock was set to OFF in SCFW, now it can be used from
kernel, so add it to device nodes so that the driver can use it
properly.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Add new dts and dtsi file for virtual i2c driver on i.MX8QXP and i.MX8QM
board.
Merge fsl-imx8qm/8qxp-mek-m4.dts to fsl-imx8qm/8qxp-mek-rpmsg.dtsi. So
delete these two files.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Currently, the phy_ref clock is also used by dsi_bridge nodes (nwl-dsi
driver) in order to set the phy_ref rate needed by a specific mode.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Add dma configurations in dts files, for imx7ulp and imx8qm.
There is no "edma0" node in fsl-imx8qm-mek(or lpddr4-arm2)-domu.dts.
lpspi0 node has been deleted in these dts files, so delete lpspi3 node.
Add edma0a and edma0d for lpspi0 and lpspi3, and enable lpspi0/3 for xen.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Acked-by: Fugang Duan <Fugang.duan@nxp.com>
Add mub-partition property for partition reset notification.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
- reserve per dev dma pool for imx rpmsg
- move imx8 rpmsg dts node to the -m4 dts files.
- re-allocate the vpu rpc reserved memory on qm mek domu dts.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
On QM the DSP is inside the VPU subsystem while in QXP
it is inside the Audio DMA subsystem. For this reason
there are "subtle" differences.
Introduce new compatible string for QM to help us correctly
configure the DSP depending on the board they run.
dsp_mem_msg structure is shared with the DSP, so by introducing
new member dsp_board_type we can let DSP know on which target it runs.
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
When DSP power domain is powered up we also need to power up IRQ steer
domain in order to receive interrupts from Audio peripherals.
Now the PD hierarchy looks like this:
* pd_dsp_irqsteer
* pd_dsp_mu_A
* pd_dsp_mu_B
* pd_dsp_ram
* pd_dsp
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
For lpspi test, add these two features, use lpspi3 without cs-gpio.
Still support spi-nor using lpspi0 with cs-gpio mode.
- fsl-imx8qm-device.dtsi:
Add node to support lpspi3.
- fsl-imx8qm-lpddr4-arm2-lpspi.dts:
Add lpspi3 support for imx8qm-lpddr4-arm2 board.
- fsl-imx8qm-lpddr4-arm2-lpspi-slave.dts:
Enable spi slave mode for lpspi3.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
alloc_contig_range easily return -EBUSY when try to isolate pages,
there are lots of messages with PFNs busy when run GPU tests.
[ 622.370671] alloc_contig_range: [4ea70, 4ea7c) PFNs busy
[ 626.518072] alloc_contig_range: [4ea90, 4ea9c) PFNs busy
these problems are related wht CMA migration for fragments,
need enlarge GPU reserved size to reduce CMA fragments.
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
The transceiver of FLEXCAN is regulated by i2c I/O Expander which
interrupt-parent is intmux, so we must set i2c I/O Expander power domain
as the sub power domain of the intmux.
In principle, the device tree describes the hardware, so the device tree
topology should follow the hardware structure. Here move the definition of
FLEXCAN to more suitable location.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
When early_power_on is present in power domain dtb node, it
will be powered on during resume regardless of whether the
related module is enabled or NOT, this will cause cm4_intmux
always power ON after first time resume when cm4_intmux is
NOT enabled.
So move this early_power_on property to board level dtb, ONLY
when cm4_intmux is enabled, then this property is added.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Adjust passive trip point temperature to be 20 degree C
below than the critical trip point temperature on i.MX8X
platforms.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit cefa63c1b9)
This patch adds pixel combiner nodes support for i.MX8qm DT
file and hooks the pixel combiner nodes to the DPU nodes.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
With the updated i.MX8QM silicon, prg1/10 may be shared bewteen
dpr1/3_channel1 and dpr1/3_channel2 respectively with appropriate
mux configurations in SCU firmware. If prg1/10 are attached to
dpr1/3_channel2, then they act as the auxiliary prg to process
chroma pixels for SC_R_DC_0/1_BLIT1. Otherwise, they act as the
primary prg to process RGB pixels for SC_R_DC_0/1_BLIT0.
Let's reflect this update in the device tree file.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit dab218c3c4)
Add support for i.MX8QM B0 vpu decoder and encoder and it is compatiable
with i.MX8QXP B0 VPU.
Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com>
(cherry picked from commit f2d7823da29c55644299eea84a2e866ea188c698)
We load DSP firmware from the ARM side at 0x556e8000 but because the
compiler generated memory layout starts at 0x596e8000 we need to do
some fixups.
Thus, each address (in DSP local memory) generated by the compiler
needs to be substracted an offset = 0x596e8000 - 0x556e8000 = 0x4000000.
Because this only happens on QM we will use dts to specify the offset.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 8d4518d2a5d956549e829470af15003d7adff841)
i.mx8QM B0 comes with a DSP (placed in the VPU unit).
From the ARM core side DSP local memory (Inst/Data) is mapped at
0x55000000-0x55FFFFFF range.
DSP also uses code located in SDRAM mapping starting at 0x92400000.
While at it, move rpmsg_node up in order to have all reserved
areas sorted by address.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 1eb4b2ee64c6f1fd7a5d6ceb1f019e876dbdfeb9)
Replace the M4_MU# by the LSIO MU in the RPMSG usage.
Otherwise, M4 can't enter into LPM if the M4_MU# is
used in RPMSG.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
PCIe ep rc validation system is one remote processors
communications.
Add the reserved region in pcie node, and use this region as
ddr test region in pcie ep rc validation system.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
The dpu driver may properly handle display clock parent selection now.
Thus, let's remove the assigned-clocks and assigned-clock-parents
device tree properties from the dpu device tree nodes.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Change the hdmi dig_pll clock rate to 675MHz,
hdmi core clock is source from dig_pll.
And HDMI CEC required core clock should integer MHz(675/5=135MHz).
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Ranjani Vaidyanathan