Commit Graph

3 Commits

Author SHA1 Message Date
Linus Walleij 03a127ef9b ARM: dts: Fix up the D-Link DIR-685 MTD partition info
[ Upstream commit 738a05e673 ]

The vendor firmware was analyzed to get the right idea about
this flash layout. /proc/mtd contains:

dev:    size   erasesize  name
mtd0: 01e7ff40 00020000 "rootfs"
mtd1: 01f40000 00020000 "upgrade"
mtd2: 00040000 00020000 "rgdb"
mtd3: 00020000 00020000 "nvram"
mtd4: 00040000 00020000 "RedBoot"
mtd5: 00020000 00020000 "LangPack"
mtd6: 02000000 00020000 "flash"

Here "flash" is obviously the whole device and we know "rootfs"
is a bogus hack to point to a squashfs rootfs inside of the main
"upgrade partition". We know "RedBoot" is the first 0x40000 of
the flash and the "upgrade" partition follows from 0x40000 to
0x1f8000. So we have mtd0, 1, 4 and 6 covered.

Remains:
mtd2: 00040000 00020000 "rgdb"
mtd3: 00020000 00020000 "nvram"
mtd5: 00020000 00020000 "LangPack"

Inspecting the flash at 0x1f8000 and 0x1fa000 reveals each of
these starting with "RGCFG1" so we assume 0x1f8000-1fbfff is
"rgdb" of 0x40000.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-02-12 19:46:02 +01:00
Linus Walleij f328c2eac5 ARM: dts: gemini: add pin control set-up for the SoC
This adds the basic pin control muliplexing settings for the
Gemini SoC: parallel (NOR) flash, SATA, optional IDE, PCI and
UART.

We also select the right GPIO groups on all applicable systems
so that GPIO keys/LEDs work smoothly.

We can then build upon this for more complex systems.

Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-08 14:20:00 +02:00
Linus Walleij 22789ae3bb ARM: dts: Add DTS file for D-Link DIR-685
This adds a device tree file for the Gemini-based D-Link DIR-685
router, supporting all devices that are currently supported in
the main DTSI SoC file.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-08 14:19:29 +02:00