Commit Graph

31 Commits

Author SHA1 Message Date
Yang Yingliang ff4d21fb22 PCI: endpoint: Fix missing destroy_workqueue()
[ Upstream commit acaef7981a218813e3617edb9c01837808de063c ]

Add the missing destroy_workqueue() before return from
pci_epf_test_init() in the error handling case and add
destroy_workqueue() in pci_epf_test_exit().

Link: https://lore.kernel.org/r/20210331084012.2091010-1-yangyingliang@huawei.com
Fixes: 349e7a85b2 ("PCI: endpoint: functions: Add an EP function to test PCI")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-05-19 10:08:25 +02:00
Alan Mikhak dbb7bbcc8a PCI: endpoint: Clear BAR before freeing its space
Associated pci_epf_bar structure is needed in pci_epc_clear_bar() to
clear a BAR correctly but it is reset in pci_epf_free_space() (that
is called first) which results in pci_epc_clear_bar() failure.

Reorder the pci_epc_clear_bar()/pci_epf_free_space() calls execution
to fix the issue.

Signed-off-by: Alan Mikhak <alan.mikhak@sifive.com>
[lorenzo.pieralisi@arm.com: reworded the commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-06-11 10:57:54 +01:00
Alan Mikhak 3041a64361 PCI: endpoint: Skip odd BAR when skipping 64bit BAR
Always skip odd BAR when skipping 64bit BARs in pci_epf_test_set_bar()
and pci_epf_test_alloc_space() otherwise pci_epf_test_set_bar() will
call pci_epc_set_bar() on an odd loop index when skipping reserved 64bit
BAR.

Moreover, pci_epf_test_alloc_space() will call pci_epf_alloc_space() on
bind for an odd loop index when BAR is 64bit but leaks on subsequent
unbind by not calling pci_epf_free_space().

Signed-off-by: Alan Mikhak <alan.mikhak@sifive.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Paul Walmsley <paul.walmsley@sifive.com>
2019-06-11 10:55:36 +01:00
Alan Mikhak f16fb16ed1 PCI: endpoint: Allocate enough space for fixed size BAR
PCI endpoint test function code should honor the .bar_fixed_size parameter
from underlying endpoint controller drivers or results may be unexpected.

In pci_epf_test_alloc_space(), check if BAR being used for test
register space is a fixed size BAR. If so, allocate the required fixed
size.

Signed-off-by: Alan Mikhak <alan.mikhak@sifive.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-06-11 10:55:22 +01:00
Bjorn Helgaas ee6df38da8 Merge branch 'remotes/lorenzo/pci/misc'
- Exit pcitest with error code when test fails (Jean-Jacques Hiblot)

  - Fix leaked of_node references in dra7xx, uniphier, layerscape,
    rockchip, aardvark, iproc, mediatek, rpadlpar (Wen Yang)

  - Fix pcitest "help" option parsing (Kishon Vijay Abraham I)

  - Fix Makefile bug that inadvertently removes pcitest.sh (Kishon Vijay
    Abraham I)

  - Check for alloc_workqueue() failure in endpoint test driver (Kangjie
    Lu)

* remotes/lorenzo/pci/misc:
  PCI: endpoint: Fix a potential NULL pointer dereference
  tools: PCI: Handle pcitest.sh independently from pcitest
  tools: PCI: Add 'h' in optstring of getopt()
  PCI: mediatek: Fix a leaked reference by adding missing of_node_put()
  PCI: iproc: Fix a leaked reference by adding missing of_node_put()
  PCI: aardvark: Fix a leaked reference by adding missing of_node_put()
  PCI: rockchip: Fix a leaked reference by adding missing of_node_put()
  PCI: dwc: layerscape: Fix a leaked reference by adding missing of_node_put()
  PCI: uniphier: Fix a leaked reference by adding missing of_node_put()
  PCI: dwc: pci-dra7xx: Fix a leaked reference by adding missing of_node_put()
  tools: PCI: Exit with error code when test fails
2019-05-13 18:34:44 -05:00
Kishon Vijay Abraham I 2a9a801620 PCI: endpoint: Add support to specify alignment for buffers allocated to BARs
The address that is allocated using pci_epf_alloc_space() is
directly written to the target address of the Inbound Address
Translation unit (ie the HW component implementing inbound address
decoding) on endpoint controllers.

Designware IP [1] has a configuration parameter (CX_ATU_MIN_REGION_SIZE
[2]) which has 64KB as default value and the lower 16 bits of the Base,
Limit and Target registers of the Inbound ATU are fixed to zero. If the
programmed memory address is not aligned to 64 KB boundary this causes
memory corruption.

Modify pci_epf_alloc_space() API to take alignment size as argument in
order to allocate buffers to be mapped to BARs with an alignment that
suits the platform where they are used.

Add an 'align' parameter to epc_features which can be used by platform
drivers to specify the BAR allocation alignment requirements and use
this while invoking pci_epf_alloc_space().

[1] "I/O and MEM Match Modes" section in DesignWare Cores PCI Express
     Controller Databook version 4.90a
[2]  http://www.ti.com/lit/ug/spruid7c/spruid7c.pdf

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2019-04-15 13:24:02 +01:00
Kangjie Lu 507b820009 PCI: endpoint: Fix a potential NULL pointer dereference
In case alloc_workqueue() fails, return -ENOMEM to avoid
potential NULL pointer dereferences.

Signed-off-by: Kangjie Lu <kjlu@umn.edu>
[lorenzo.pieralisi@arm.com: commit log and code update]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2019-04-12 15:25:09 +01:00
Kishon Vijay Abraham I 2c04c5b8ee PCI: pci-epf-test: Use pci_epc_get_features() to get EPC features
Use pci_epc_get_features() to get EPC features such as linkup
notifier support, MSI/MSIX capable, BAR configuration etc and use it
for configuring pci-epf-test. Since these features are now obtained
directly from EPC driver, remove pci_epf_test_data which was initially
added to have EPC features in endpoint function driver.

Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2019-02-15 10:01:16 +00:00
Kishon Vijay Abraham I b866c56b66 PCI: pci-epf-test: Do not allocate next BARs memory if current BAR is 64Bit
It's useless to allocate memory for next BAR if the current BAR is a
64Bit BAR. Stop allocating memory for the next BAR, if the current
BARs flag indicates this is a 64Bit BAR.

Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2019-02-15 10:00:18 +00:00
Kishon Vijay Abraham I 0342e9a797 PCI: pci-epf-test: Remove setting epf_bar flags in function driver
Now that pci_epf_alloc_space() sets BAR MEM TYPE flags as 64Bit or
32Bit based on size, remove setting it in function driver.

Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2019-02-15 10:00:09 +00:00
Wen Yang 726dabfde6 PCI: endpoint: functions: Use memcpy_fromio()/memcpy_toio()
Functions copying from/to IO addresses should use the
memcpy_fromio()/memcpy_toio() API rather than plain memcpy().

Fix the issue detected through the sparse tool.

Fixes: 349e7a85b2 ("PCI: endpoint: functions: Add an EP function to test PCI")
Suggested-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Wen Yang <wen.yang99@zte.com.cn>
[lorenzo.pieralisi@arm.com: updated log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
CC: Bjorn Helgaas <bhelgaas@google.com>
CC: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
CC: Niklas Cassel <niklas.cassel@axis.com>
CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
CC: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
CC: linux-pci@vger.kernel.org
CC: linux-kernel@vger.kernel.org
2019-02-13 09:50:58 +00:00
Gustavo Pimentel c2e00e3108 pci-epf-test/pci_endpoint_test: Add MSI-X support
Add MSI-X support and update driver documentation accordingly.

Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-07-19 11:46:45 +01:00
Gustavo Pimentel e8817de7fb pci-epf-test/pci_endpoint_test: Cleanup PCI_ENDPOINT_TEST memspace
Cleanup PCI_ENDPOINT_TEST memspace (by moving the interrupt number away
from command section).

Add IRQ_TYPE register to identify the triggered ID interrupt required
for the READ/WRITE/COPY tests and raise IRQ test commands.

Update documentation accordingly.

Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-07-19 11:39:44 +01:00
Bjorn Helgaas bf79d7d099 Merge branch 'lorenzo/pci/endpoint'
- use usleep() instead of mdelay() in endpoint test (Jia-Ju Bai)

  - add configfs entries for pci_epf_driver device IDs (Kishon Vijay
    Abraham I)

  - clean up pci_endpoint_test driver (Gustavo Pimentel)

* lorenzo/pci/endpoint:
  PCI: endpoint: Create configfs entry for each pci_epf_device_id table entry
  misc: pci_endpoint_test: Use pci_irq_vector function
  PCI: endpoint: functions/pci-epf-test: Replace lower into upper case characters
  misc: pci_endpoint_test: Replace lower into upper case characters
  PCI: endpoint: Replace mdelay with usleep_range() in pci_epf_test_write()
2018-06-06 16:10:30 -05:00
Gustavo Pimentel 1d906b2207 PCI: dwc: Add support for EP mode
The PCIe controller dual mode is capable of operating in Root Complex
(RC) mode as well as EP mode by configuration option.

Add EP support to the DesignWare driver on top of RC mode support.

Add new property on pci_epc structure which allow to configure
pci_epf_test driver accordingly to the controller specific requirements.

Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-05-15 15:51:38 +01:00
Gustavo Pimentel 798c0441be PCI: endpoint: functions/pci-epf-test: Replace lower into upper case characters
Replace all initial lower case character into upper case in comments
and debug printks.

Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2018-05-15 15:13:10 +01:00
Jia-Ju Bai 9f96b9b7d8 PCI: endpoint: Replace mdelay with usleep_range() in pci_epf_test_write()
pci_epf_test_write() is never called in atomic context.

The call chain ending up at pci_epf_test_write() is:
[1] pci_epf_test_write() <- pci_epf_test_cmd_handler()

pci_epf_test_cmd_handler() is set as a parameter of INIT_DELAYED_WORK()
in pci_epf_test_probe().
This function is not called in atomic context.

Despite never getting called from atomic context, pci_epf_test_write()
calls mdelay() to busy wait.

This is not necessary and can be replaced with usleep_range() to
avoid busy waiting.

Signed-off-by: Jia-Ju Bai <baijiaju1990@gmail.com>
[lorenzo.pieralisi@arm.com: updated commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-05-08 11:13:42 +01:00
Niklas Cassel 77d08dbdae PCI: endpoint: Make epc->ops->clear_bar()/pci_epc_clear_bar() take struct *epf_bar
Make epc->ops->clear_bar()/pci_epc_clear_bar() take struct *epf_bar.

This is needed so that epc->ops->clear_bar() can clear the BAR pair,
if the BAR is 64-bits wide.

This also makes it possible for pci_epc_clear_bar() to sanity check
the flags.

Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
2018-04-03 12:38:05 +01:00
Niklas Cassel fca8305875 PCI: endpoint: Handle 64-bit BARs properly
If a 64-bit BAR was set-up, we need to skip a BAR,
since a 64-bit BAR consists of a BAR pair.

We need to check what BAR width the epc->ops->set_bar() specific
implementation actually did set-up, since some drivers, like the
Cadence EP controller, sometimes sets up a 64-bit BAR, even though
a 32-bit BAR was requested.

Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-04-03 12:38:04 +01:00
Niklas Cassel bc4a48976f PCI: endpoint: Simplify epc->ops->set_bar()/pci_epc_set_bar()
Add barno and flags to struct epf_bar.
That way we can simplify epc->ops->set_bar()/pci_epc_set_bar()
by passing a struct *epf_bar instead of a whole lot of arguments.

This is needed so that epc->ops->set_bar() implementations can
modify BAR flags. Will be utilized in a succeeding patch.

Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-04-03 12:23:38 +01:00
Niklas Cassel bf597574b6 PCI: endpoint: BAR width should not depend on sizeof dma_addr_t
If a BAR supports 64-bit width or not depends on the hardware,
and should thus not depend on sizeof(dma_addr_t).

If a certain hardware doesn't support 64-bit BARs, its
epc->ops->set_bar() implementation should return -EINVAL
when PCI_BASE_ADDRESS_MEM_TYPE_64 is set.

We can't change pci_epc_set_bar() to only set
PCI_BASE_ADDRESS_MEM_TYPE_64 based on size, since if the user,
for some reason, wants to configure a BAR with a 64-bit width,
even though the BAR size is less than 4 GB, he should be able
to do that.

However, since pci-epf-test is simply a test and not an API,
we can set PCI_BASE_ADDRESS_MEM_TYPE_64 in pci-epf-test itself
only based on size.

Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-04-03 12:23:30 +01:00
Bjorn Helgaas ab8c609356 Merge branch 'pci/spdx' into next
* pci/spdx:
  PCI: Add SPDX GPL-2.0+ to replace implicit GPL v2 or later statement
  PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplate
  PCI: Add SPDX GPL-2.0 to replace COPYING boilerplate
  PCI: Add SPDX GPL-2.0 to replace GPL v2 boilerplate
  PCI: Add SPDX GPL-2.0 when no license was specified
2018-02-01 11:40:07 -06:00
Cyrille Pitchen 4494738de0 PCI: endpoint: Add the function number as argument to EPC ops
This patch updates the prototype of most handlers from 'struct
pci_epc_ops' so the EPC library can now support multi-function devices.

Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2018-01-31 11:10:41 +00:00
Bjorn Helgaas 8cfab3cf63 PCI: Add SPDX GPL-2.0 to replace GPL v2 boilerplate
Add SPDX GPL-2.0 to all PCI files that specified the GPL version 2 license.

Remove the boilerplate GPL version 2 language, relying on the assertion in
b24413180f ("License cleanup: add SPDX GPL-2.0 license identifier to
files with no license") that the SPDX identifier may be used instead of the
full boilerplate text.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-01-28 15:48:29 -06:00
John Keeping 749aaf3372 PCI: endpoint: Use correct "end of test" interrupt
pci_epf_test_raise_irq() reads the interrupt to use for the response from
reg->command, but this has been cleared at the beginning of the command
handler so the value is always zero at this point.

Instead, extract the interrupt index before handling the command and then
pass the requested interrupt into pci_epf_test_raise_irq().  This allows us
to remove the specific code to extract the interrupt for
COMMAND_RAISE_MSI_IRQ since it is now handled in common code.

Fixes: 3ecf3232c5 ("PCI: endpoint: Do not reset *command* inadvertently")
Signed-off-by: John Keeping <john@metanate.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-09-20 13:56:06 -05:00
Shawn Lin 2ca93ffa93 PCI: endpoint: Remove the ->remove() callback
epf_test is allocated using devm_kzalloc(). Hence it's not required to
explicitly free it in remove() callback. Since ->remove() callback doesn't
do anything other than freeing epf_test, remove the ->remove() callback.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-29 16:00:38 -05:00
Kishon Vijay Abraham I 702a3ed9d6 PCI: endpoint: Add support to poll early for host commands
Certain platforms like TI's K2G doesn't support link-up notification. Add
support to poll early (without waiting for the linkup notification) for
commands from the host.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-29 16:00:38 -05:00
Kishon Vijay Abraham I 3235b99495 PCI: endpoint: Add support to use _any_ BAR to map PCI_ENDPOINT_TEST regs
pci_epf_test always maps the PCI_ENDPOINT_TEST registers to BAR_0. But if
BAR_0 is reserved for some other purpose (like in TI's K2G BAR_0 is mapped
to application registers and cannot be used to map any other regions),
PCI_ENDPOINT_TEST registers cannot be mapped making pci_epf_test unusable.
Add support to use any BAR to map PCI_ENDPOINT_TEST registers.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-29 16:00:37 -05:00
Kishon Vijay Abraham I 3ecf3232c5 PCI: endpoint: Do not reset *command* inadvertently
pci_epf_test_cmd_handler() is the delayed work function which reads
*command* (set by the host) and performs various actions requested by the
host periodically. If the value in *command* is '0', it goes to the
reset_handler where it resets *command* to '0' and queues
pci_epf_test_cmd_handler().

However if the host writes a value to the *command* just after the
pci-epf-test driver checks *command* for '0' and before the control goes to
reset_handler, the *command* will be reset to '0' and the pci-epf-test
driver won't be able to perform the actions requested by the host.  Fix it
here by not resetting the *command* in the reset_handler.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-29 16:00:37 -05:00
Kishon Vijay Abraham I 09232c7acb PCI: endpoint: Add "volatile" to pci_epf_test_reg
struct pci_epf_test_reg is the MEMSPACE of pci-epf-test function driver
that will be accessed by the "host" for programming the pci-epf-test
device. So this structure shouldn't be subjected to compiler optimization
in pci_epf_test_cmd_handler() since the values can be changed by code
outside the scope of current code at any time.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-29 16:00:37 -05:00
Kishon Vijay Abraham I 349e7a85b2 PCI: endpoint: functions: Add an EP function to test PCI
Adds a new endpoint function driver (to program the virtual test device)
making use of the EP-core library.

[bhelgaas: fold in pci_epf_test_probe() -ENOMEM test from Wei Yongjun
<weiyongjun1@huawei.com>]
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-04-11 14:18:37 -05:00