Add the M4 core reset for i.MX8MQ, then we could use reset API
to start/stop M4.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
There is hardware issue: TKT0535653
SDMA3 can't work without setting AUDIOMIX_CLKEN0[SDMA2] (bit-26) to 1
The workaround is:
As the reset state of AUDIOMIX_CLKEN0[SDMA2] is enabled,
we just need to keep it on as reset state, don't touch it
in kernel, then every thing is same as before, if we register
the clock in clk-audiomix, then kernel will try to disable
it in idle.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
This patch adds "media_ldb_root_clk" clock for
the LDB in the MEDIAMIX subsystem.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds DISP2 pixel clock for the second instance of LCDIFv3
in the MEDIAMIX subsystem.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Add driver for imx8dxl based on previous SCU implementations.
Signed-off-by: Teo Hall <teo.hall@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
commit 4881873f4cc1460f63d85fa81363d56be328ccdc upstream.
According to the public S805 datasheet the RESET2 register uses the
following bits for the PIC_DC, PSC and NAND reset lines:
- PIC_DC is at bit 3 (meaning: RESET_VD_RMEM + 3)
- PSC is at bit 4 (meaning: RESET_VD_RMEM + 4)
- NAND is at bit 5 (meaning: RESET_VD_RMEM + 4)
Update the reset IDs of these three reset lines so they don't conflict
with PIC_DC and map to the actual hardware reset lines.
Fixes: 79795e20a1 ("dt-bindings: reset: Add bindings for the Meson SoC Reset Controller")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The root clock slice at 0xbf00 is media_ldb clock, not csi_phy2_ref,
so correct it.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
The audiomix MFD driver registers some devices, one of which maps correctly to
a reset controller type. This driver registers a reset controller for that.
For now, only the EARC specific resets are added.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
A53 CCM clk root only accepts input up to 1GHz, however
the A53 core could run above 1GHz which voliates the CCM limitation.
There is a CORE_SEL slice before A53 core, we need configure the
CORE_SEL slice source from ARM PLL, not A53 CCM clk root.
The A53 CCM clk root should only be used when need to change ARM PLL
frequency.
Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out.
Configure a53 ccm root sources from 800MHz sys pll
Configure a53 core sources from arm_pll_out
Enable arm_pll_out to avoid disable the clock when set a53 core parent.
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
A53 CCM clk root only accepts input up to 1GHz, however
the A53 core could run above 1GHz which voliates the CCM limitation.
There is a CORE_SEL slice before A53 core, we need configure the
CORE_SEL slice source from ARM PLL, not A53 CCM clk root.
The A53 CCM clk root should only be used when need to change ARM PLL
frequency.
Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out.
Configure a53 ccm root sources from 800MHz sys pll
Configure a53 core sources from arm_pll_out
Enable arm_pll_out to avoid disable the clock when set a53 core parent.
Fixes: 96d6392b54 ("clk: imx: Add support for i.MX8MN clock driver")
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
A53 CCM clk root only accepts input up to 1GHz, however
the A53 core could run above 1GHz which voliates the CCM limitation.
There is a CORE_SEL slice before A53 core, we need configure the
CORE_SEL slice source from ARM PLL, not A53 CCM clk root.
The A53 CCM clk root should only be used when need to change ARM PLL
frequency.
Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out.
Configure a53 ccm root sources from 800MHz sys pll
Configure a53 core sources from arm_pll_out
Enable arm_pll_out to avoid disable the clock when set a53 core parent.
Fixes: ba5625c3e2 ("clk: imx: Add clock driver support for imx8mm")
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
A53 CCM clk root only accepts input up to 1GHz, however
the A53 core could run above 1GHz which voliates the CCM limitation.
There is a CORE_SEL slice before A53 core, we need configure the
CORE_SEL slice source from ARM PLL, not A53 CCM clk root.
The A53 CCM clk root should only be used when need to change ARM PLL
frequency.
Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out.
Configure a53 ccm root sources from 800MHz sys pll
Configure a53 core sources from arm_pll_out
Enable arm_pll_out to avoid disable the clock when set a53 core parent.
Fixes db27e40b27 ("clk: imx8mq: Add the missing ARM clock")
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Current i2c4/uart1 clocks ID have conflict with pwm2/pwm3,
correct them.
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
* reset/next: (12 commits)
reset: Kconfig: use 'ARCH_MXC' for reset dispmix
reset: imx8m: Correct clock name for dispmix driver
reset: gpio-reset: add pinctrl comsuer header file
reset: imx7: add the clkreq reset for imx8m
dt-bindings: reset: imx7: add clkreq reset used by the l1ss on imx8m
...
* pcie/next: (40 commits)
LF-128 PCI: imx: turn off the clocks and regulators when link is down
PCI: imx: add the imx pcie ep verification solution
misc: pci_endpoint_test: Add the layerscape PCIe GEN4 EP device support
PCI: mobiveil: Add workaround for unsupported request error
PCI: mobiveil: Add PCIe Gen4 EP driver for NXP Layerscape SoCs
...
* dts/next: (765 commits)
arm64: dts: fsl: ls1028a: Disable eno3 and make swp5 the Felix CPU port
arm64: dts: fsl: ls1028a: Specify that the Felix port 4 runs at 2.5Gbps
arm64: dts: fsl: Drop "compatible" string from Felix switch
arm64: dts: fsl: Specify phy-mode for CPU ports
LF-261: arm64: dts: imx8mq: Set parent clock for IMX8MQ_CLK_AUDIO_AHB
...
Define macros for the combinations of MSCR numbers and values to be
written into those registers. These will be used together in 'fsl,pins'
properties of pinctrl group dts nodes.
Signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com>
Signed-off-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
The values of the s32v234_pins enum from pinctrl-s32v234.c will be moved
to s32v234-pinctrl.h to avoid using magic numbers in ENET configuration
definitions.
Signed-off-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Add ethernet clocks and dependencies (sys_pll, arm_pll)
Based on ALB v4.19.31_bsp23.0_rc2
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Enable the clocks needed for LINFlexD UART support on Treerunner and make
use of them in the LINFlexD driver.
Signed-off-by: Stoica Cosmin-Stefan <cosmin.stoica@nxp.com>
Signed-off-by: Adrian.Nitu <adrian.nitu@freescale.com>
Signed-off-by: Larisa Grigore <Larisa.Grigore@nxp.com>
Signed-off-by: Iustin Dumitrescu <Iustin.Dumitrescu@nxp.com>
Signed-off-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com>
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Add DT bindings documentation for the upcoming S32V234 clk driver. Add
s32v234-clock.h header, which is referred in MC_CGM documentation.
Signed-off-by: Stoica Cosmin-Stefan <cosmin.stoica@nxp.com>
Signed-off-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com>
This patch forwards some IPUv3 and LDB clock changes from imx_4.19.y kernel,
as needed to enable internal IPUv3 fb and LVDS displays.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The mipi pll clock comes from the MIPI PHY PLL output, so
it should not be a fixed clock.
MIPI PHY PLL is in the MIPI DSI space, and it is used as
the bit clock for transfering the pixel data out and its
output clock is configured according to the display mode.
So it should be used only for MIPI DSI and not be exported
out for other usages.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
The ENET RMII 50M SCU Ref clock was wrongly put in LPCG clock ID
definition which may overwrite the SCU clock IDs.
Fix it by move it into the correct place.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Stéphane Dion