Commit Graph

28 Commits

Author SHA1 Message Date
Thomas Gleixner d2912cb15b treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500
Based on 2 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-19 17:09:55 +02:00
Thomas Gleixner 1802d0beec treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation this program is
  distributed in the hope that it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 655 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-30 11:26:41 -07:00
Christoph Hellwig eb01d42a77 PCI: consolidate PCI config entry in drivers/pci
There is no good reason to duplicate the PCI menu in every architecture.
Instead provide a selectable HAVE_PCI symbol that indicates availability
of PCI support, and a FORCE_PCI symbol to for PCI on and the handle the
rest in drivers/pci.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Paul Burton <paul.burton@mips.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-23 11:45:34 +09:00
Eugeniy Paltsev d7de73b586 ARC: [plat-axs103] refactor the quad core DT quirk code
Refactor the quad core DT quirk code:
get rid of waste division and multiplication by 1000000 constant.

Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2017-12-20 12:41:45 -08:00
Eugeniy Paltsev fbd1cec570 ARC: [plat-axs103]: Set initial core pll output frequency
Set initial core pll output frequency specified in device tree to
100MHz for SMP configuration and 90MHz for UP configuration.
It will be applied at the core pll driver probing.

Update platform quirk for decreasing core frequency for quad core
configuration.

Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2017-12-20 12:41:45 -08:00
Eugeniy Paltsev ff64d695f9 ARC: [plat-axs10x] DTS: Add reset controller node to manage ethernet reset
DW ethernet controller on axs10x hangs sometimes after SW reset.
Invoke the newly aded driver (reset-axs10x.c) by adding the DT bits.

With this in place, we don't need the open-coded quirk in platform
code, so get rid of it as well !

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2017-11-15 09:40:43 -08:00
Vineet Gupta 4fbaf649eb ARC: [plat-axs10x] auto-select AXS101 or AXS103 given the ISA config
AXS10x platform has two flavours:
 - AXS101 (ARC700 cpu, ARCompact ISA)
 - AXS103 (ARC HS38x cpu, ARCv2 ISA)

So depending on the ISA support configured, pre-select the AXS10x
variant.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2017-10-29 16:19:30 -07:00
Eugeniy Paltsev 043d1e729b ARC: [plat-axs103] Add temporary quirk to reset ethernet IP
DW ethernet controller on AXS10x hangs sometimes after SW reset, so
add temporary quirk to reset DW ethernet controller IP core.
This quirk can be removed after axs10x reset driver
(see http://patchwork.ozlabs.org/patch/800273/)
or simple reset driver
(see https://patchwork.kernel.org/patch/9903375/)
will be available in upstream.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2017-10-03 20:36:49 -07:00
Vineet Gupta 0fa400cb8a ARC: [plat-axs103] refactor the DT fudging code
with clk frequency setting code gone by prev commits, we can elide the
unconditonal DT parsing to the specific case of quad core config where
we possibly need to fudge the DT value.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2017-09-01 11:26:26 -07:00
Eugeniy Paltsev 9926c29f74 ARC: [plat-axs103] use clk driver #1: Get rid of platform specific cpu clk setting
historically axs103 platform code used to set the cpu clk by writing to
PLL registers directly. however the axs10x clk driver is now upstream so
no need to do this amymore.

Driver is selected automatically when CONFIG_ARC_PLAT_AXS10X is set

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
[vgupta: deleted more code not needed anymore]
2017-09-01 11:26:24 -07:00
Vineet Gupta 2d7f5c48c0 ARC: move mcip.h into include/soc and adjust the includes
Also remove the dependency on ARCv2, to increase compile coverage for
!ARCV2 builds

Acked-by: Daniel Lezcano <daniel.lezcnao@linaro.org>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-11-30 11:54:25 -08:00
Linus Torvalds 0efacbbaee ARC updates for 4.7-rc1
- Support for EZChip (now Mellanox) NPS-400 Network processor based on ARC700
     http://www.mellanox.com/related-docs/prod_npu/PB_NPS-400.pdf
 - NPS interrupt controller and clocksource drivers
 - ARC timers probed off DT
 - ARC iqrchips switching to linear domain (upgrade from legacy domains)
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Merge tag 'arc-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc

Pull ARC updates from Vineet Gupta:
 "We have a relatively big changeset for ARC for 4.7.

  The highlight is support for EZChip (now Mellanox) NPS-400 network
  processor, a 400-Gb throughput C-programmable packet processor based
  on ARC700 cores from Synopsys. See

        http://www.mellanox.com/related-docs/prod_npu/PB_NPS-400.pdf

  Also present are irqchip and clocksource drivers for NPS as agreed
  with respective maintainers to go via ARC tree due to an soc header
  dependency.  I have the needed ACKs from Jason, Marc, Daniel.  You
  might run into a trivial merge conflict in drivers/irqchip/*

  This EZChip platform support required some deep changes in ARC
  architecture code and also opportunity to cleanup past sins (legacy
  irq domains, missing irq domain lookup, hard coded timer irqs...)

  Summary:

   - Support for EZChip (now Mellanox) NPS-400 Network processor based
     on ARC700

   - NPS interrupt controller and clocksource drivers

   - ARC timers probed off DT

   - ARC iqrchips switching to linear domain (upgrade from legacy
     domains)"

* tag 'arc-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (37 commits)
  arc: axs103_smp: Fix CPU frequency to 100MHz for dual-core
  arc: axs10x: Add DT bindings for I2S PLL Clock
  ARC: pae: STRICT_MM_TYPECHECKS was broken
  ARC: Add eznps platform to Kconfig and Makefile
  ARC: [plat-eznps] Use dedicated COMMAND_LINE_SIZE
  ARC: [plat-eznps] Use dedicated cpu_relax()
  ARC: [plat-eznps] Use dedicated identity auxiliary register.
  ARC: [plat-eznps] Use dedicated SMP barriers
  ARC: [plat-eznps] Use dedicated atomic/bitops/cmpxchg
  ARC: [plat-eznps] Use dedicated user stack top
  ARC: [plat-eznps] Add eznps platform
  ARC: [plat-eznps] Add eznps board defconfig and dts
  ARC: Mark secondary cpu online only after all HW setup is done
  ARC: rwlock: disable interrupts in !LLSC variant
  ARC: Make vmalloc size configurable
  ARC: clean out UAPI byteorder.h clean off Kconfig symbol
  irqchip: add nps Internal and external irqchips
  clocksource: Add NPS400 timers driver
  soc: Support for EZchip SoC
  Documentation: Add EZchip vendor to binding list
  ...
2016-05-19 09:46:18 -07:00
Alexey Brodkin 776d7f1694 arc: axs103_smp: Fix CPU frequency to 100MHz for dual-core
The most recent release of AXS103 [v1.1] is proven to work
at 100 MHz in dual-core mode so this change uses mentioned feature.
For that we:
 * Update axc003_idu.dtsi with mention of really-used CPU clock freq
 * Remove clock override in AXS platform code for dual-core HW

Note we're still leaving a hack for clock "downgrade" on early boot
for quad-core hardware.

Also note this change will break functionality of AXS103 v1.0 hardware.
That means all users of AXS103 __must__ upgrade their boards with the
most recent firmware.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-18 10:50:18 +05:30
Alexey Brodkin 20c7dbbdbe ARC: Don't try to use value of top level clock-frequency in DT
We no longer use it and instead a real clk device such as fixed-clk
instance is fed to timers etc.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
[vgupta: broken out of a bigger patch, rewrote changelog]
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09 09:32:30 +05:30
Vineet Gupta b3d6aba8bd ARC: [dts] Add clk feeding into timers to DTs
This allows us to introduce timers in DT in next commit

The core clk frequency hack in AXS103 platform is also extended,
where the core clk feeding into timers is updated in-place in FDT.

Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09 09:32:29 +05:30
Vineet Gupta 0eeb3dfe4b ARC: [plat-axs] Refactor core freq get/set
Reduces diff in future patches !

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09 09:32:28 +05:30
Linus Walleij 59851aa87c arc: select GPIOLIB directly
Instead of indirectly selecting GPIOLIB via the
ARCH_REQUIRE_GPIOLIB symbol, just select GPIOLIB.

Cc: Michael Büsch <m@bues.ch>
Cc: linux-snps-arc@lists.infradead.org
Acked-by: Vineet Gupta <vgupt@synopsys.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-04-26 14:07:59 +02:00
Joao Pinto c1678ffcde ARC: Add PCI support
Add PCI support to ARC and update drivers/pci Makefile enabling the ARC
arch to use the generic PCI setup functions.

[bhelgaas: fold in Joao's pci-dma-compat.h & pci-bridge.h build fix (I
should have caught this myself, sorry]
Signed-off-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Vineet Gupta <vgupta@synopsys.com>
2016-03-10 14:44:13 -06:00
Vineet Gupta aa0efcde45 ARCv2: smp: [plat-*]: No need to explicitly call mcip_init_smp()
MCIP now registers it's own per cpu setup routine (for IPI IRQ request)
using smp_ops.init_irq_cpu().

So no need for platforms to do that. This now completely decouples
platforms from MCIP.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-28 16:13:41 +05:30
Vineet Gupta 26b8f99623 ARCv2: smp: [plat-*]: No need to explicitly call mcip_init_early_smp()
MCIP now registers it's own probe callback with smp_ops.init_early_smp()
which is called by ARC common code, so no need for platforms to do that.

This decouples the platforms and MCIP and helps confine MCIP details
to it's own file.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-28 16:13:40 +05:30
Vineet Gupta 3ebb0540c2 ARCv2: [axs103_smp] Reduce clk for SMP FPGA configs
Newer bitfiles needs the reduced clk even for SMP builds

Cc: <stable@vger.kernel.org>  #4.2
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2015-09-11 19:34:01 -07:00
Vineet Gupta 090749502f ARC: add/fix some comments in code - no functional change
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-08-20 19:05:49 +05:30
Vineet Gupta 6de7abfbad ARCv2: [axs103_smp] Reduce clk for Quad FPGA configs
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-08-04 09:26:30 +05:30
Ruud Derwig 2924cd18c4 ARCv2: [vdk] dts files and defconfig for HS38 VDK
- CONFIG_ARC_UBOOT_SUPPORT to handle arguments passed in r0, r1, r2
 - CONFIG_DEVTMPFS_MOUNT for mouting rootfs since it uses external cpio
   for rootfs

Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Ruud Derwig <rderwig@synopsys.com>
[vgupta: folded the Main baord DT files for smp/up into one]
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-25 06:00:21 +05:30
Vineet Gupta 5fa2daaa8d ARCv2: [axs103] Support ARC SDP FPGA platform for HS38x cores
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-25 06:00:20 +05:30
Vineet Gupta db7e985526 ARC: [axs101] Add missing __init annotations
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:32 +05:30
Vineet Gupta 749aa0e11a ARC: [axs101] Tweak DDR port aperture mappings for performance
Route all MB originated traffic to DDR Port 1 and keep Port 0 for CPU
traffic only

Basic system parameters
--------------------------------------------------------------------------------------
        Host                 OS Description 				Mhz  tlb   cache  mem   scal
                                                			    pages  line   par   load
                                                      				   bytes
----------------- ------------- --------------------------------------- ---- ----- ----- ------ ----
axs101-sd-2-new-f Linux 3.13.0+ axs101-sd-2-new-fw-old-img-rerun    	739  	8    32 1.1100    1
axs101-sd-3-arc-3 Linux 3.13.9+ axs101-sd-3-arc-3.13-tip-regression 	735  	8    32 1.1000    1
axs101-sd-9-diffe Linux 3.13.11 axs101-sd-9-different-tweak         	740  	8    32 1.0000    1

Processor, Processes - times in microseconds - smaller is better
------------------------------------------------------------------------------
Host                 OS  Mhz null null      open slct sig  sig  fork exec sh
                             call  I/O stat clos TCP  inst hndl proc proc proc
--------- ------------- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
axs101-sd Linux 3.13.0+  739 0.50 0.88 5.38 14.6 34.1 0.92 5.18 2135 6555 12.K
axs101-sd Linux 3.13.9+  735 0.50 0.90 5.89 19.2 81.4 0.94 4.08 2560 8559 15.K
axs101-sd Linux 3.13.11  740 0.50 0.88 4.45 17.8 34.4 0.94 3.25 2052 6493 12.K
                                                 ^^^^                     ^^^^

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:31 +05:30
Alexey Brodkin 556cc1c5f5 ARC: [axs101] Add support for AXS101 SDP (software development platform)
The AXS10x platforms consist of a mainboard with peripherals,
on which several daughter cards can be placed. The daughter cards
typically contain a CPU and memory.

Signed-off-by: Mischa Jonker <mjonker@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19 18:09:30 +05:30