arm64: dts: qcom: msm8998: Disable coresight by default
commit a636f93fcdb4a516e7cba6a365645ee8429602b2 upstream.
Boot failure has been reported on MSM8998 based laptop when
coresight is enabled. This is most likely due to lack of
firmware support for coresight on production device when
compared to debug device like MTP where this issue is not
observed. So disable coresight by default for MSM8998 and
enable it only for MSM8998 MTP.
Reported-and-tested-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Fixes: 783abfa224 ("arm64: dts: qcom: msm8998: Add Coresight support")
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Sai Prakash Ranjan
Greg Kroah-Hartman
parent
ac7f852e21
commit
f690a8ced5
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@ -27,6 +27,66 @@
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status = "okay";
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};
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&etf {
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status = "okay";
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};
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&etm1 {
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status = "okay";
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};
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&etm2 {
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status = "okay";
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};
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&etm3 {
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status = "okay";
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};
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&etm4 {
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status = "okay";
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};
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&etm5 {
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status = "okay";
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};
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&etm6 {
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status = "okay";
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};
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&etm7 {
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status = "okay";
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};
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&etm8 {
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status = "okay";
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};
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&etr {
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status = "okay";
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};
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&funnel1 {
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status = "okay";
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};
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&funnel2 {
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status = "okay";
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};
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&funnel3 {
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status = "okay";
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};
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&funnel4 {
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status = "okay";
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};
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&funnel5 {
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status = "okay";
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};
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&pm8005_lsid1 {
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pm8005-regulators {
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compatible = "qcom,pm8005-regulators";
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@ -51,6 +111,10 @@
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vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
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};
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&replicator1 {
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status = "okay";
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};
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&rpm_requests {
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pm8998-regulators {
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compatible = "qcom,rpm-pm8998-regulators";
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@ -249,6 +313,10 @@
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pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
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};
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&stm {
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status = "okay";
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};
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&ufshc {
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vcc-supply = <&vreg_l20a_2p95>;
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vccq-supply = <&vreg_l26a_1p2>;
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@ -998,11 +998,12 @@
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#interrupt-cells = <0x2>;
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};
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stm@6002000 {
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stm: stm@6002000 {
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compatible = "arm,coresight-stm", "arm,primecell";
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reg = <0x06002000 0x1000>,
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<0x16280000 0x180000>;
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reg-names = "stm-base", "stm-data-base";
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status = "disabled";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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@ -1016,9 +1017,10 @@
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};
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};
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funnel@6041000 {
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funnel1: funnel@6041000 {
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
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reg = <0x06041000 0x1000>;
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status = "disabled";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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@ -1045,9 +1047,10 @@
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};
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};
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funnel@6042000 {
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funnel2: funnel@6042000 {
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
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reg = <0x06042000 0x1000>;
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status = "disabled";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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@ -1075,9 +1078,10 @@
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};
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};
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funnel@6045000 {
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funnel3: funnel@6045000 {
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
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reg = <0x06045000 0x1000>;
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status = "disabled";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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@ -1113,9 +1117,10 @@
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};
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};
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replicator@6046000 {
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replicator1: replicator@6046000 {
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compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
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reg = <0x06046000 0x1000>;
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status = "disabled";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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@ -1137,9 +1142,10 @@
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};
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};
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etf@6047000 {
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etf: etf@6047000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0x06047000 0x1000>;
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status = "disabled";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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@ -1163,9 +1169,10 @@
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};
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};
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etr@6048000 {
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etr: etr@6048000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0x06048000 0x1000>;
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status = "disabled";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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@ -1181,9 +1188,10 @@
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};
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};
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etm@7840000 {
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etm1: etm@7840000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0x07840000 0x1000>;
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status = "disabled";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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@ -1200,9 +1208,10 @@
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};
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};
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etm@7940000 {
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etm2: etm@7940000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0x07940000 0x1000>;
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status = "disabled";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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@ -1219,9 +1228,10 @@
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};
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};
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etm@7a40000 {
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etm3: etm@7a40000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0x07a40000 0x1000>;
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status = "disabled";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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@ -1238,9 +1248,10 @@
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};
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};
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etm@7b40000 {
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etm4: etm@7b40000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0x07b40000 0x1000>;
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status = "disabled";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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@ -1257,9 +1268,10 @@
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};
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};
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funnel@7b60000 { /* APSS Funnel */
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funnel4: funnel@7b60000 { /* APSS Funnel */
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0x07b60000 0x1000>;
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status = "disabled";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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@ -1343,9 +1355,10 @@
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};
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};
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funnel@7b70000 {
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funnel5: funnel@7b70000 {
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
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reg = <0x07b70000 0x1000>;
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status = "disabled";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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@ -1369,9 +1382,10 @@
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};
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};
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etm@7c40000 {
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etm5: etm@7c40000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0x07c40000 0x1000>;
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status = "disabled";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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@ -1385,9 +1399,10 @@
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};
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};
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etm@7d40000 {
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etm6: etm@7d40000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0x07d40000 0x1000>;
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status = "disabled";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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@ -1401,9 +1416,10 @@
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};
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};
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etm@7e40000 {
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etm7: etm@7e40000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0x07e40000 0x1000>;
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status = "disabled";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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@ -1417,9 +1433,10 @@
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};
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};
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etm@7f40000 {
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etm8: etm@7f40000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0x07f40000 0x1000>;
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status = "disabled";
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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