MLKU-38-3 crypto: caam - add SNVS / SECVIO support
This is a squash of the following i.MX BSP commits
(rel_imx_4.19.35_1.1.0_rc2)
1. 8f6a17b41917 ("ENGR00289885 [iMX6Q] Add Secure Memory and SECVIO support.")
2. 8433c811e97a ("MLK-9710-18 snvs - make SECVIO module device tree correct")
3. 35bbc34e996b ("MLK-9769-23 Replace SECVIO of_irq_to_resource() with irq_of_parse_and_map()")
4. 3ac6edcd92d4 ("MLK-11360-01 crypto: caam_snvs: add snvs clock management")
5. 9d9ca7a03e3b ("MLK-11922 i.mx6: Linux 3.14.28 CAAM & SNVS enabled by default. JTAG, DS-5 attachment causes exceptions")
6. fcdaabf1bba2 ("MLK-17412-01: Fix secvio driver to have same driver name as DTS")
Signed-off-by: Dan Douglass <dan.douglass@nxp.com>
Signed-off-by: Victoria Milhoan <vicki.milhoan@freescale.com>
Signed-off-by: Steve Cornelius <steve.cornelius@nxp.com>
Signed-off-by: Fugang Duan <andy.duan@nxp.com>
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
that have been reworked:
1.
-make SM depend on JR
-enable SM, SECVIO only on i.MX SoCs
-fix resource leak - add off_node_put() where needed
Split commit in three:
- SNVS/SECVIO driver
- Secure Memory driver
- DT changes
3.
JR changes dropped - no longer needed, already upstream in
commit 549077d7d8 ("crypto: caam - check irq_of_parse_and_map for errors")
4.
Split the patch in two:
-DT bindings changes
-driver changes
5.
Fixed conflicts in imx7d.dtsi - added caam_sm and irq_sec_vio nodes.
Split commit in 3:
-SECVIO/SNVS driver changes
-SECVIO/SNVS DT changes
-Secure Memory DT changes
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
This commit is contained in:
Horia Geantă
Dong Aisheng
parent
6aa9b70c99
commit
f50dd756a0
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@ -155,6 +155,13 @@ config CRYPTO_DEV_FSL_CAAM_RNG_TEST
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caam RNG. This test is several minutes long and executes
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just before the RNG is registered with the hw_random API.
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config CRYPTO_DEV_FSL_CAAM_SECVIO
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tristate "CAAM/SNVS Security Violation Handler (EXPERIMENTAL)"
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help
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Enables installation of an interrupt handler with registrable
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handler functions which can be specified to act on the consequences
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of a security violation.
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endif # CRYPTO_DEV_FSL_CAAM_JR
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endif # CRYPTO_DEV_FSL_CAAM
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@ -21,6 +21,7 @@ caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI) += caamalg_qi.o
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caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API) += caamhash.o
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caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API) += caamrng.o
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caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API) += caampkc.o pkc_desc.o
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caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO) += secvio.o
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caam-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI) += qi.o
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ifneq ($(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI),)
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@ -719,9 +719,6 @@ iomap_ctrl:
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BLOCK_OFFSET * DECO_BLOCK_NUMBER
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);
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/* Get the IRQ of the controller (for security violations only) */
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ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
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if (!reg_access)
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goto set_dma_mask;
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@ -66,6 +66,7 @@ struct caam_drv_private_jr {
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* Driver-private storage for a single CAAM block instance
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*/
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struct caam_drv_private {
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/* Physical-presence section */
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struct caam_ctrl __iomem *ctrl; /* controller region */
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struct caam_deco __iomem *deco; /* DECO/CCB views */
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@ -83,8 +84,7 @@ struct caam_drv_private {
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u8 qi_present; /* Nonzero if QI present in device */
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u8 mc_en; /* Nonzero if MC f/w is active */
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u8 scu_en; /* Nonzero if SCU f/w is active */
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+ u8 optee_en; /* Nonzero if OP-TEE f/w is active */
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int secvio_irq; /* Security violation interrupt number */
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u8 optee_en; /* Nonzero if OP-TEE f/w is active */
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int virt_en; /* Virtualization enabled in CAAM */
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int era; /* CAAM Era (internal HW revision) */
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@ -0,0 +1,342 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* SNVS Security Violation Handler
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*
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* Copyright 2012-2016 Freescale Semiconductor, Inc.
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* Copyright 2017-2019 NXP
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*/
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#include "compat.h"
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#include "secvio.h"
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#include "regs.h"
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#include "intern.h"
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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/* The driver is matched with node caam_snvs to get regmap
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* It will then retrieve interruption and tamper alarm configuration from
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* node caam-secvio searching for the compat string "fsl,imx6q-caam-secvio"
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*/
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#define DRIVER_NAME "caam-snvs"
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/*
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* These names are associated with each violation handler.
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* The source names were taken from MX6, and are based on recommendations
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* for most common SoCs.
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*/
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static const u8 *violation_src_name[] = {
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"CAAM Internal Security Violation",
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"JTAG Alarm",
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"Watchdog",
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"(reserved)",
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"External Boot",
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"External Tamper Detect",
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};
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/* These names help describe security monitor state for the console */
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static const u8 *snvs_ssm_state_name[] = {
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"init",
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"hard fail",
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"(undef:2)",
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"soft fail",
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"(undef:4)",
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"(undef:5)",
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"(undef:6)",
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"(undef:7)",
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"transition",
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"check",
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"(undef:10)",
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"non-secure",
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"(undef:12)",
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"trusted",
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"(undef:14)",
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"secure",
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};
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/* Top-level security violation interrupt */
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static irqreturn_t snvs_secvio_interrupt(int irq, void *snvsdev)
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{
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struct device *dev = snvsdev;
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struct snvs_secvio_drv_private *svpriv = dev_get_drvdata(dev);
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clk_enable(svpriv->clk);
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/* Check the HP secvio status register */
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svpriv->irqcause = rd_reg32(&svpriv->svregs->hp.secvio_status) &
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HP_SECVIOST_SECVIOMASK;
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if (!svpriv->irqcause) {
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clk_disable(svpriv->clk);
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return IRQ_NONE;
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}
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/* Now ACK cause */
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clrsetbits_32(&svpriv->svregs->hp.secvio_status, 0, svpriv->irqcause);
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/* And run deferred service */
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preempt_disable();
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tasklet_schedule(&svpriv->irqtask[smp_processor_id()]);
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preempt_enable();
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clk_disable(svpriv->clk);
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return IRQ_HANDLED;
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}
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/* Deferred service handler. Tasklet arg is simply the SNVS dev */
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static void snvs_secvio_dispatch(unsigned long indev)
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{
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struct device *dev = (struct device *)indev;
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struct snvs_secvio_drv_private *svpriv = dev_get_drvdata(dev);
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unsigned long flags;
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int i;
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/* Look through stored causes, call each handler if exists */
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for (i = 0; i < MAX_SECVIO_SOURCES; i++)
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if (svpriv->irqcause & (1 << i)) {
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spin_lock_irqsave(&svpriv->svlock, flags);
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svpriv->intsrc[i].handler(dev, i,
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svpriv->intsrc[i].ext);
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spin_unlock_irqrestore(&svpriv->svlock, flags);
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};
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/* Re-enable now-serviced interrupts */
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clrsetbits_32(&svpriv->svregs->hp.secvio_intcfg, 0, svpriv->irqcause);
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}
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/*
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* Default cause handler, used in lieu of an application-defined handler.
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* All it does at this time is print a console message. It could force a halt.
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*/
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static void snvs_secvio_default(struct device *dev, u32 cause, void *ext)
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{
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struct snvs_secvio_drv_private *svpriv = dev_get_drvdata(dev);
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dev_err(dev, "Unhandled Security Violation Interrupt %d = %s\n",
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cause, svpriv->intsrc[cause].intname);
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}
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/*
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* Install an application-defined handler for a specified cause
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* Arguments:
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* - dev points to SNVS-owning device
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* - cause interrupt source cause
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* - handler application-defined handler, gets called with dev
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* source cause, and locally-defined handler argument
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* - cause_description points to a string to override the default cause
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* name, this can be used as an alternate for error
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* messages and such. If left NULL, the default
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* description string is used.
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* - ext pointer to any extra data needed by the handler.
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*/
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int snvs_secvio_install_handler(struct device *dev, enum secvio_cause cause,
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void (*handler)(struct device *dev, u32 cause,
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void *ext),
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u8 *cause_description, void *ext)
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{
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unsigned long flags;
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struct snvs_secvio_drv_private *svpriv;
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svpriv = dev_get_drvdata(dev);
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if ((handler == NULL) || (cause > SECVIO_CAUSE_SOURCE_5))
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return -EINVAL;
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spin_lock_irqsave(&svpriv->svlock, flags);
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svpriv->intsrc[cause].handler = handler;
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if (cause_description != NULL)
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svpriv->intsrc[cause].intname = cause_description;
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if (ext != NULL)
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svpriv->intsrc[cause].ext = ext;
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spin_unlock_irqrestore(&svpriv->svlock, flags);
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return 0;
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}
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EXPORT_SYMBOL(snvs_secvio_install_handler);
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/*
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* Remove an application-defined handler for a specified cause (and, by
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* implication, restore the "default".
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* Arguments:
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* - dev points to SNVS-owning device
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* - cause interrupt source cause
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*/
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int snvs_secvio_remove_handler(struct device *dev, enum secvio_cause cause)
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{
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unsigned long flags;
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struct snvs_secvio_drv_private *svpriv;
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svpriv = dev_get_drvdata(dev);
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if (cause > SECVIO_CAUSE_SOURCE_5)
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return -EINVAL;
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spin_lock_irqsave(&svpriv->svlock, flags);
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svpriv->intsrc[cause].intname = violation_src_name[cause];
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svpriv->intsrc[cause].handler = snvs_secvio_default;
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svpriv->intsrc[cause].ext = NULL;
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spin_unlock_irqrestore(&svpriv->svlock, flags);
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return 0;
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}
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EXPORT_SYMBOL(snvs_secvio_remove_handler);
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static int snvs_secvio_remove(struct platform_device *pdev)
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{
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struct device *svdev;
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struct snvs_secvio_drv_private *svpriv;
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int i;
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svdev = &pdev->dev;
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svpriv = dev_get_drvdata(svdev);
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clk_enable(svpriv->clk);
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/* Set all sources to nonfatal */
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wr_reg32(&svpriv->svregs->hp.secvio_intcfg, 0);
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/* Remove tasklets and release interrupt */
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for_each_possible_cpu(i)
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tasklet_kill(&svpriv->irqtask[i]);
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clk_disable_unprepare(svpriv->clk);
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free_irq(svpriv->irq, svdev);
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iounmap(svpriv->svregs);
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kfree(svpriv);
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return 0;
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}
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static int snvs_secvio_probe(struct platform_device *pdev)
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{
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struct device *svdev;
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struct snvs_secvio_drv_private *svpriv;
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struct device_node *np, *npirq;
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struct snvs_full __iomem *snvsregs;
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int i, error;
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u32 hpstate;
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const void *jtd, *wtd, *itd, *etd;
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u32 td_en;
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svpriv = kzalloc(sizeof(struct snvs_secvio_drv_private), GFP_KERNEL);
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if (!svpriv)
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return -ENOMEM;
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svdev = &pdev->dev;
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dev_set_drvdata(svdev, svpriv);
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svpriv->pdev = pdev;
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np = pdev->dev.of_node;
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npirq = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-secvio");
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if (!npirq) {
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dev_err(svdev, "can't find secvio node\n");
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kfree(svpriv);
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return -EINVAL;
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}
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svpriv->irq = irq_of_parse_and_map(npirq, 0);
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if (svpriv->irq <= 0) {
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dev_err(svdev, "can't identify secvio interrupt\n");
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kfree(svpriv);
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return -EINVAL;
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}
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jtd = of_get_property(npirq, "jtag-tamper", NULL);
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wtd = of_get_property(npirq, "watchdog-tamper", NULL);
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itd = of_get_property(npirq, "internal-boot-tamper", NULL);
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etd = of_get_property(npirq, "external-pin-tamper", NULL);
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if (!jtd | !wtd | !itd | !etd ) {
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dev_err(svdev, "can't identify all tamper alarm configuration\n");
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kfree(svpriv);
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return -EINVAL;
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}
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/*
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* Configure all sources according to device tree property.
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* If the property is enabled then the source is ser as
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* fatal violations except LP section,
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* source #5 (typically used as an external tamper detect), and
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* source #3 (typically unused). Whenever the transition to
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* secure mode has occurred, these will now be "fatal" violations
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*/
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td_en = HP_SECVIO_INTEN_SRC0;
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if (!strcmp(jtd, "enabled"))
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td_en |= HP_SECVIO_INTEN_SRC1;
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if (!strcmp(wtd, "enabled"))
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td_en |= HP_SECVIO_INTEN_SRC2;
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if (!strcmp(itd, "enabled"))
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td_en |= HP_SECVIO_INTEN_SRC4;
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if (!strcmp(etd, "enabled"))
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td_en |= HP_SECVIO_INTEN_SRC5;
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snvsregs = of_iomap(np, 0);
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if (!snvsregs) {
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dev_err(svdev, "register mapping failed\n");
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return -ENOMEM;
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}
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svpriv->svregs = (struct snvs_full __force *)snvsregs;
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svpriv->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(svpriv->clk)) {
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dev_err(&pdev->dev, "can't get snvs clock\n");
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svpriv->clk = NULL;
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}
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/* Write the Secvio Enable Config the SVCR */
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wr_reg32(&svpriv->svregs->hp.secvio_ctl, td_en);
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wr_reg32(&svpriv->svregs->hp.secvio_intcfg, td_en);
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/* Device data set up. Now init interrupt source descriptions */
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for (i = 0; i < MAX_SECVIO_SOURCES; i++) {
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svpriv->intsrc[i].intname = violation_src_name[i];
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svpriv->intsrc[i].handler = snvs_secvio_default;
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}
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/* Connect main handler */
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for_each_possible_cpu(i)
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tasklet_init(&svpriv->irqtask[i], snvs_secvio_dispatch,
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(unsigned long)svdev);
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error = request_irq(svpriv->irq, snvs_secvio_interrupt,
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IRQF_SHARED, DRIVER_NAME, svdev);
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if (error) {
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dev_err(svdev, "can't connect secvio interrupt\n");
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irq_dispose_mapping(svpriv->irq);
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svpriv->irq = 0;
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iounmap(svpriv->svregs);
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kfree(svpriv);
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return -EINVAL;
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}
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clk_prepare_enable(svpriv->clk);
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hpstate = (rd_reg32(&svpriv->svregs->hp.status) &
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HP_STATUS_SSM_ST_MASK) >> HP_STATUS_SSM_ST_SHIFT;
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dev_info(svdev, "violation handlers armed - %s state\n",
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snvs_ssm_state_name[hpstate]);
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clk_disable(svpriv->clk);
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return 0;
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}
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static struct of_device_id snvs_secvio_match[] = {
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{
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.compatible = "fsl,imx6q-caam-snvs",
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, snvs_secvio_match);
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static struct platform_driver snvs_secvio_driver = {
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.driver = {
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.name = DRIVER_NAME,
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.owner = THIS_MODULE,
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.of_match_table = snvs_secvio_match,
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},
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.probe = snvs_secvio_probe,
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.remove = snvs_secvio_remove,
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};
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module_platform_driver(snvs_secvio_driver);
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MODULE_LICENSE("Dual BSD/GPL");
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MODULE_DESCRIPTION("FSL SNVS Security Violation Handler");
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MODULE_AUTHOR("Freescale Semiconductor - MCU");
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@ -0,0 +1,69 @@
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/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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/*
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* CAAM Security Violation Handler
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*
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* Copyright 2012-2015 Freescale Semiconductor, Inc.
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* Copyright 2016-2019 NXP
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*/
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#ifndef SECVIO_H
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#define SECVIO_H
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#include "snvsregs.h"
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/*
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* Defines the published interfaces to install/remove application-specified
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* handlers for catching violations
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*/
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|
||||
#define MAX_SECVIO_SOURCES 6
|
||||
|
||||
/* these are the untranslated causes */
|
||||
enum secvio_cause {
|
||||
SECVIO_CAUSE_SOURCE_0,
|
||||
SECVIO_CAUSE_SOURCE_1,
|
||||
SECVIO_CAUSE_SOURCE_2,
|
||||
SECVIO_CAUSE_SOURCE_3,
|
||||
SECVIO_CAUSE_SOURCE_4,
|
||||
SECVIO_CAUSE_SOURCE_5
|
||||
};
|
||||
|
||||
/* These are common "recommended" cause definitions for most devices */
|
||||
#define SECVIO_CAUSE_CAAM_VIOLATION SECVIO_CAUSE_SOURCE_0
|
||||
#define SECVIO_CAUSE_JTAG_ALARM SECVIO_CAUSE_SOURCE_1
|
||||
#define SECVIO_CAUSE_WATCHDOG SECVIO_CAUSE_SOURCE_2
|
||||
#define SECVIO_CAUSE_EXTERNAL_BOOT SECVIO_CAUSE_SOURCE_4
|
||||
#define SECVIO_CAUSE_TAMPER_DETECT SECVIO_CAUSE_SOURCE_5
|
||||
|
||||
int snvs_secvio_install_handler(struct device *dev, enum secvio_cause cause,
|
||||
void (*handler)(struct device *dev, u32 cause,
|
||||
void *ext),
|
||||
u8 *cause_description, void *ext);
|
||||
int snvs_secvio_remove_handler(struct device *dev, enum secvio_cause cause);
|
||||
|
||||
/*
|
||||
* Private data definitions for the secvio "driver"
|
||||
*/
|
||||
|
||||
struct secvio_int_src {
|
||||
const u8 *intname; /* Points to a descriptive name for source */
|
||||
void *ext; /* Extended data to pass to the handler */
|
||||
void (*handler)(struct device *dev, u32 cause, void *ext);
|
||||
};
|
||||
|
||||
struct snvs_secvio_drv_private {
|
||||
struct platform_device *pdev;
|
||||
spinlock_t svlock ____cacheline_aligned;
|
||||
struct tasklet_struct irqtask[NR_CPUS];
|
||||
struct snvs_full __iomem *svregs; /* both HP and LP domains */
|
||||
struct clk *clk;
|
||||
int irq;
|
||||
u32 irqcause; /* stashed cause of violation interrupt */
|
||||
|
||||
/* Registered handlers for each violation */
|
||||
struct secvio_int_src intsrc[MAX_SECVIO_SOURCES];
|
||||
|
||||
};
|
||||
|
||||
#endif /* SECVIO_H */
|
||||
|
|
@ -0,0 +1,239 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
|
||||
/*
|
||||
* SNVS hardware register-level view
|
||||
*
|
||||
* Copyright 2012-2015 Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2019 NXP
|
||||
*/
|
||||
|
||||
#ifndef SNVSREGS_H
|
||||
#define SNVSREGS_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
/*
|
||||
* SNVS High Power Domain
|
||||
* Includes security violations, HA counter, RTC, alarm
|
||||
*/
|
||||
struct snvs_hp {
|
||||
u32 lock; /* HPLR - HP Lock */
|
||||
u32 cmd; /* HPCOMR - HP Command */
|
||||
u32 ctl; /* HPCR - HP Control */
|
||||
u32 secvio_intcfg; /* HPSICR - Security Violation Int Config */
|
||||
u32 secvio_ctl; /* HPSVCR - Security Violation Control */
|
||||
u32 status; /* HPSR - HP Status */
|
||||
u32 secvio_status; /* HPSVSR - Security Violation Status */
|
||||
u32 ha_counteriv; /* High Assurance Counter IV */
|
||||
u32 ha_counter; /* High Assurance Counter */
|
||||
u32 rtc_msb; /* Real Time Clock/Counter MSB */
|
||||
u32 rtc_lsb; /* Real Time Counter LSB */
|
||||
u32 time_alarm_msb; /* Time Alarm MSB */
|
||||
u32 time_alarm_lsb; /* Time Alarm LSB */
|
||||
};
|
||||
|
||||
#define HP_LOCK_HAC_LCK 0x00040000
|
||||
#define HP_LOCK_HPSICR_LCK 0x00020000
|
||||
#define HP_LOCK_HPSVCR_LCK 0x00010000
|
||||
#define HP_LOCK_MKEYSEL_LCK 0x00000200
|
||||
#define HP_LOCK_TAMPCFG_LCK 0x00000100
|
||||
#define HP_LOCK_TAMPFLT_LCK 0x00000080
|
||||
#define HP_LOCK_SECVIO_LCK 0x00000040
|
||||
#define HP_LOCK_GENP_LCK 0x00000020
|
||||
#define HP_LOCK_MONOCTR_LCK 0x00000010
|
||||
#define HP_LOCK_CALIB_LCK 0x00000008
|
||||
#define HP_LOCK_SRTC_LCK 0x00000004
|
||||
#define HP_LOCK_ZMK_RD_LCK 0x00000002
|
||||
#define HP_LOCK_ZMK_WT_LCK 0x00000001
|
||||
|
||||
#define HP_CMD_NONPRIV_AXS 0x80000000
|
||||
#define HP_CMD_HAC_STOP 0x00080000
|
||||
#define HP_CMD_HAC_CLEAR 0x00040000
|
||||
#define HP_CMD_HAC_LOAD 0x00020000
|
||||
#define HP_CMD_HAC_CFG_EN 0x00010000
|
||||
#define HP_CMD_SNVS_MSTR_KEY 0x00002000
|
||||
#define HP_CMD_PROG_ZMK 0x00001000
|
||||
#define HP_CMD_SW_LPSV 0x00000400
|
||||
#define HP_CMD_SW_FSV 0x00000200
|
||||
#define HP_CMD_SW_SV 0x00000100
|
||||
#define HP_CMD_LP_SWR_DIS 0x00000020
|
||||
#define HP_CMD_LP_SWR 0x00000010
|
||||
#define HP_CMD_SSM_SFNS_DIS 0x00000004
|
||||
#define HP_CMD_SSM_ST_DIS 0x00000002
|
||||
#define HP_CMD_SMM_ST 0x00000001
|
||||
|
||||
#define HP_CTL_TIME_SYNC 0x00010000
|
||||
#define HP_CTL_CAL_VAL_SHIFT 10
|
||||
#define HP_CTL_CAL_VAL_MASK (0x1f << HP_CTL_CALIB_SHIFT)
|
||||
#define HP_CTL_CALIB_EN 0x00000100
|
||||
#define HP_CTL_PI_FREQ_SHIFT 4
|
||||
#define HP_CTL_PI_FREQ_MASK (0xf << HP_CTL_PI_FREQ_SHIFT)
|
||||
#define HP_CTL_PI_EN 0x00000008
|
||||
#define HP_CTL_TIMEALARM_EN 0x00000002
|
||||
#define HP_CTL_RTC_EN 0x00000001
|
||||
|
||||
#define HP_SECVIO_INTEN_EN 0x10000000
|
||||
#define HP_SECVIO_INTEN_SRC5 0x00000020
|
||||
#define HP_SECVIO_INTEN_SRC4 0x00000010
|
||||
#define HP_SECVIO_INTEN_SRC3 0x00000008
|
||||
#define HP_SECVIO_INTEN_SRC2 0x00000004
|
||||
#define HP_SECVIO_INTEN_SRC1 0x00000002
|
||||
#define HP_SECVIO_INTEN_SRC0 0x00000001
|
||||
#define HP_SECVIO_INTEN_ALL 0x8000003f
|
||||
|
||||
#define HP_SECVIO_ICTL_CFG_SHIFT 30
|
||||
#define HP_SECVIO_ICTL_CFG_MASK (0x3 << HP_SECVIO_ICTL_CFG_SHIFT)
|
||||
#define HP_SECVIO_ICTL_CFG5_SHIFT 5
|
||||
#define HP_SECVIO_ICTL_CFG5_MASK (0x3 << HP_SECVIO_ICTL_CFG5_SHIFT)
|
||||
#define HP_SECVIO_ICTL_CFG_DISABLE 0
|
||||
#define HP_SECVIO_ICTL_CFG_NONFATAL 1
|
||||
#define HP_SECVIO_ICTL_CFG_FATAL 2
|
||||
#define HP_SECVIO_ICTL_CFG4_FATAL 0x00000010
|
||||
#define HP_SECVIO_ICTL_CFG3_FATAL 0x00000008
|
||||
#define HP_SECVIO_ICTL_CFG2_FATAL 0x00000004
|
||||
#define HP_SECVIO_ICTL_CFG1_FATAL 0x00000002
|
||||
#define HP_SECVIO_ICTL_CFG0_FATAL 0x00000001
|
||||
|
||||
#define HP_STATUS_ZMK_ZERO 0x80000000
|
||||
#define HP_STATUS_OTPMK_ZERO 0x08000000
|
||||
#define HP_STATUS_OTPMK_SYN_SHIFT 16
|
||||
#define HP_STATUS_OTPMK_SYN_MASK (0x1ff << HP_STATUS_OTPMK_SYN_SHIFT)
|
||||
#define HP_STATUS_SSM_ST_SHIFT 8
|
||||
#define HP_STATUS_SSM_ST_MASK (0xf << HP_STATUS_SSM_ST_SHIFT)
|
||||
#define HP_STATUS_SSM_ST_INIT 0
|
||||
#define HP_STATUS_SSM_ST_HARDFAIL 1
|
||||
#define HP_STATUS_SSM_ST_SOFTFAIL 3
|
||||
#define HP_STATUS_SSM_ST_INITINT 8
|
||||
#define HP_STATUS_SSM_ST_CHECK 9
|
||||
#define HP_STATUS_SSM_ST_NONSECURE 11
|
||||
#define HP_STATUS_SSM_ST_TRUSTED 13
|
||||
#define HP_STATUS_SSM_ST_SECURE 15
|
||||
|
||||
#define HP_SECVIOST_ZMK_ECC_FAIL 0x08000000 /* write to clear */
|
||||
#define HP_SECVIOST_ZMK_SYN_SHIFT 16
|
||||
#define HP_SECVIOST_ZMK_SYN_MASK (0x1ff << HP_SECVIOST_ZMK_SYN_SHIFT)
|
||||
#define HP_SECVIOST_SECVIO5 0x00000020
|
||||
#define HP_SECVIOST_SECVIO4 0x00000010
|
||||
#define HP_SECVIOST_SECVIO3 0x00000008
|
||||
#define HP_SECVIOST_SECVIO2 0x00000004
|
||||
#define HP_SECVIOST_SECVIO1 0x00000002
|
||||
#define HP_SECVIOST_SECVIO0 0x00000001
|
||||
#define HP_SECVIOST_SECVIOMASK 0x0000003f
|
||||
|
||||
/*
|
||||
* SNVS Low Power Domain
|
||||
* Includes glitch detector, SRTC, alarm, monotonic counter, ZMK
|
||||
*/
|
||||
struct snvs_lp {
|
||||
u32 lock;
|
||||
u32 ctl;
|
||||
u32 mstr_key_ctl; /* Master Key Control */
|
||||
u32 secvio_ctl; /* Security Violation Control */
|
||||
u32 tamper_filt_cfg; /* Tamper Glitch Filters Configuration */
|
||||
u32 tamper_det_cfg; /* Tamper Detectors Configuration */
|
||||
u32 status;
|
||||
u32 srtc_msb; /* Secure Real Time Clock/Counter MSB */
|
||||
u32 srtc_lsb; /* Secure Real Time Clock/Counter LSB */
|
||||
u32 time_alarm; /* Time Alarm */
|
||||
u32 smc_msb; /* Secure Monotonic Counter MSB */
|
||||
u32 smc_lsb; /* Secure Monotonic Counter LSB */
|
||||
u32 pwr_glitch_det; /* Power Glitch Detector */
|
||||
u32 gen_purpose;
|
||||
u32 zmk[8]; /* Zeroizable Master Key */
|
||||
};
|
||||
|
||||
#define LP_LOCK_MKEYSEL_LCK 0x00000200
|
||||
#define LP_LOCK_TAMPDET_LCK 0x00000100
|
||||
#define LP_LOCK_TAMPFLT_LCK 0x00000080
|
||||
#define LP_LOCK_SECVIO_LCK 0x00000040
|
||||
#define LP_LOCK_GENP_LCK 0x00000020
|
||||
#define LP_LOCK_MONOCTR_LCK 0x00000010
|
||||
#define LP_LOCK_CALIB_LCK 0x00000008
|
||||
#define LP_LOCK_SRTC_LCK 0x00000004
|
||||
#define LP_LOCK_ZMK_RD_LCK 0x00000002
|
||||
#define LP_LOCK_ZMK_WT_LCK 0x00000001
|
||||
|
||||
#define LP_CTL_CAL_VAL_SHIFT 10
|
||||
#define LP_CTL_CAL_VAL_MASK (0x1f << LP_CTL_CAL_VAL_SHIFT)
|
||||
#define LP_CTL_CALIB_EN 0x00000100
|
||||
#define LP_CTL_SRTC_INVAL_EN 0x00000010
|
||||
#define LP_CTL_WAKE_INT_EN 0x00000008
|
||||
#define LP_CTL_MONOCTR_EN 0x00000004
|
||||
#define LP_CTL_TIMEALARM_EN 0x00000002
|
||||
#define LP_CTL_SRTC_EN 0x00000001
|
||||
|
||||
#define LP_MKEYCTL_ZMKECC_SHIFT 8
|
||||
#define LP_MKEYCTL_ZMKECC_MASK (0xff << LP_MKEYCTL_ZMKECC_SHIFT)
|
||||
#define LP_MKEYCTL_ZMKECC_EN 0x00000010
|
||||
#define LP_MKEYCTL_ZMKECC_VAL 0x00000008
|
||||
#define LP_MKEYCTL_ZMKECC_PROG 0x00000004
|
||||
#define LP_MKEYCTL_MKSEL_SHIFT 0
|
||||
#define LP_MKEYCTL_MKSEL_MASK (3 << LP_MKEYCTL_MKSEL_SHIFT)
|
||||
#define LP_MKEYCTL_MK_OTP 0
|
||||
#define LP_MKEYCTL_MK_ZMK 2
|
||||
#define LP_MKEYCTL_MK_COMB 3
|
||||
|
||||
#define LP_SECVIO_CTL_SRC5 0x20
|
||||
#define LP_SECVIO_CTL_SRC4 0x10
|
||||
#define LP_SECVIO_CTL_SRC3 0x08
|
||||
#define LP_SECVIO_CTL_SRC2 0x04
|
||||
#define LP_SECVIO_CTL_SRC1 0x02
|
||||
#define LP_SECVIO_CTL_SRC0 0x01
|
||||
|
||||
#define LP_TAMPFILT_EXT2_EN 0x80000000
|
||||
#define LP_TAMPFILT_EXT2_SHIFT 24
|
||||
#define LP_TAMPFILT_EXT2_MASK (0x1f << LP_TAMPFILT_EXT2_SHIFT)
|
||||
#define LP_TAMPFILT_EXT1_EN 0x00800000
|
||||
#define LP_TAMPFILT_EXT1_SHIFT 16
|
||||
#define LP_TAMPFILT_EXT1_MASK (0x1f << LP_TAMPFILT_EXT1_SHIFT)
|
||||
#define LP_TAMPFILT_WM_EN 0x00000080
|
||||
#define LP_TAMPFILT_WM_SHIFT 0
|
||||
#define LP_TAMPFILT_WM_MASK (0x1f << LP_TAMPFILT_WM_SHIFT)
|
||||
|
||||
#define LP_TAMPDET_OSC_BPS 0x10000000
|
||||
#define LP_TAMPDET_VRC_SHIFT 24
|
||||
#define LP_TAMPDET_VRC_MASK (3 << LP_TAMPFILT_VRC_SHIFT)
|
||||
#define LP_TAMPDET_HTDC_SHIFT 20
|
||||
#define LP_TAMPDET_HTDC_MASK (3 << LP_TAMPFILT_HTDC_SHIFT)
|
||||
#define LP_TAMPDET_LTDC_SHIFT 16
|
||||
#define LP_TAMPDET_LTDC_MASK (3 << LP_TAMPFILT_LTDC_SHIFT)
|
||||
#define LP_TAMPDET_POR_OBS 0x00008000
|
||||
#define LP_TAMPDET_PFD_OBS 0x00004000
|
||||
#define LP_TAMPDET_ET2_EN 0x00000400
|
||||
#define LP_TAMPDET_ET1_EN 0x00000200
|
||||
#define LP_TAMPDET_WMT2_EN 0x00000100
|
||||
#define LP_TAMPDET_WMT1_EN 0x00000080
|
||||
#define LP_TAMPDET_VT_EN 0x00000040
|
||||
#define LP_TAMPDET_TT_EN 0x00000020
|
||||
#define LP_TAMPDET_CT_EN 0x00000010
|
||||
#define LP_TAMPDET_MCR_EN 0x00000004
|
||||
#define LP_TAMPDET_SRTCR_EN 0x00000002
|
||||
|
||||
#define LP_STATUS_SECURE
|
||||
#define LP_STATUS_NONSECURE
|
||||
#define LP_STATUS_SCANEXIT 0x00100000 /* all write 1 clear here on */
|
||||
#define LP_STATUS_EXT_SECVIO 0x00010000
|
||||
#define LP_STATUS_ET2 0x00000400
|
||||
#define LP_STATUS_ET1 0x00000200
|
||||
#define LP_STATUS_WMT2 0x00000100
|
||||
#define LP_STATUS_WMT1 0x00000080
|
||||
#define LP_STATUS_VTD 0x00000040
|
||||
#define LP_STATUS_TTD 0x00000020
|
||||
#define LP_STATUS_CTD 0x00000010
|
||||
#define LP_STATUS_PGD 0x00000008
|
||||
#define LP_STATUS_MCR 0x00000004
|
||||
#define LP_STATUS_SRTCR 0x00000002
|
||||
#define LP_STATUS_LPTA 0x00000001
|
||||
|
||||
/* Full SNVS register page, including version/options */
|
||||
struct snvs_full {
|
||||
struct snvs_hp hp;
|
||||
struct snvs_lp lp;
|
||||
u32 rsvd[731]; /* deadspace 0x08c-0xbf7 */
|
||||
|
||||
/* Version / Revision / Option ID space - end of register page */
|
||||
u32 vid; /* 0xbf8 HP Version ID (VID 1) */
|
||||
u32 opt_rev; /* 0xbfc HP Options / Revision (VID 2) */
|
||||
};
|
||||
|
||||
#endif /* SNVSREGS_H */
|
||||
Loading…
Reference in New Issue