arm: perf: Convert event enums to #defines
The enums are not necessary and this allows the event values to be used to construct static strings at compile time. Signed-off-by: Drew Richardson <drew.richardson@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Drew Richardson
Will Deacon
parent
b916b785af
commit
f4ab36cb10
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@ -35,133 +35,117 @@
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* but the encodings are considered to be `reserved' in the case that
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* they are not available.
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*/
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enum armv7_perf_types {
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ARMV7_PERFCTR_PMNC_SW_INCR = 0x00,
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ARMV7_PERFCTR_L1_ICACHE_REFILL = 0x01,
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ARMV7_PERFCTR_ITLB_REFILL = 0x02,
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ARMV7_PERFCTR_L1_DCACHE_REFILL = 0x03,
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ARMV7_PERFCTR_L1_DCACHE_ACCESS = 0x04,
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ARMV7_PERFCTR_DTLB_REFILL = 0x05,
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ARMV7_PERFCTR_MEM_READ = 0x06,
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ARMV7_PERFCTR_MEM_WRITE = 0x07,
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ARMV7_PERFCTR_INSTR_EXECUTED = 0x08,
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ARMV7_PERFCTR_EXC_TAKEN = 0x09,
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ARMV7_PERFCTR_EXC_EXECUTED = 0x0A,
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ARMV7_PERFCTR_CID_WRITE = 0x0B,
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#define ARMV7_PERFCTR_PMNC_SW_INCR 0x00
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#define ARMV7_PERFCTR_L1_ICACHE_REFILL 0x01
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#define ARMV7_PERFCTR_ITLB_REFILL 0x02
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#define ARMV7_PERFCTR_L1_DCACHE_REFILL 0x03
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#define ARMV7_PERFCTR_L1_DCACHE_ACCESS 0x04
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#define ARMV7_PERFCTR_DTLB_REFILL 0x05
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#define ARMV7_PERFCTR_MEM_READ 0x06
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#define ARMV7_PERFCTR_MEM_WRITE 0x07
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#define ARMV7_PERFCTR_INSTR_EXECUTED 0x08
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#define ARMV7_PERFCTR_EXC_TAKEN 0x09
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#define ARMV7_PERFCTR_EXC_EXECUTED 0x0A
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#define ARMV7_PERFCTR_CID_WRITE 0x0B
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/*
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* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
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* It counts:
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* - all (taken) branch instructions,
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* - instructions that explicitly write the PC,
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* - exception generating instructions.
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*/
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ARMV7_PERFCTR_PC_WRITE = 0x0C,
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ARMV7_PERFCTR_PC_IMM_BRANCH = 0x0D,
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ARMV7_PERFCTR_PC_PROC_RETURN = 0x0E,
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ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS = 0x0F,
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ARMV7_PERFCTR_PC_BRANCH_MIS_PRED = 0x10,
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ARMV7_PERFCTR_CLOCK_CYCLES = 0x11,
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ARMV7_PERFCTR_PC_BRANCH_PRED = 0x12,
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/*
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* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
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* It counts:
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* - all (taken) branch instructions,
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* - instructions that explicitly write the PC,
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* - exception generating instructions.
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*/
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#define ARMV7_PERFCTR_PC_WRITE 0x0C
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#define ARMV7_PERFCTR_PC_IMM_BRANCH 0x0D
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#define ARMV7_PERFCTR_PC_PROC_RETURN 0x0E
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#define ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS 0x0F
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#define ARMV7_PERFCTR_PC_BRANCH_MIS_PRED 0x10
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#define ARMV7_PERFCTR_CLOCK_CYCLES 0x11
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#define ARMV7_PERFCTR_PC_BRANCH_PRED 0x12
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/* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */
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ARMV7_PERFCTR_MEM_ACCESS = 0x13,
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ARMV7_PERFCTR_L1_ICACHE_ACCESS = 0x14,
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ARMV7_PERFCTR_L1_DCACHE_WB = 0x15,
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ARMV7_PERFCTR_L2_CACHE_ACCESS = 0x16,
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ARMV7_PERFCTR_L2_CACHE_REFILL = 0x17,
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ARMV7_PERFCTR_L2_CACHE_WB = 0x18,
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ARMV7_PERFCTR_BUS_ACCESS = 0x19,
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ARMV7_PERFCTR_MEM_ERROR = 0x1A,
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ARMV7_PERFCTR_INSTR_SPEC = 0x1B,
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ARMV7_PERFCTR_TTBR_WRITE = 0x1C,
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ARMV7_PERFCTR_BUS_CYCLES = 0x1D,
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/* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */
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#define ARMV7_PERFCTR_MEM_ACCESS 0x13
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#define ARMV7_PERFCTR_L1_ICACHE_ACCESS 0x14
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#define ARMV7_PERFCTR_L1_DCACHE_WB 0x15
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#define ARMV7_PERFCTR_L2_CACHE_ACCESS 0x16
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#define ARMV7_PERFCTR_L2_CACHE_REFILL 0x17
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#define ARMV7_PERFCTR_L2_CACHE_WB 0x18
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#define ARMV7_PERFCTR_BUS_ACCESS 0x19
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#define ARMV7_PERFCTR_MEM_ERROR 0x1A
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#define ARMV7_PERFCTR_INSTR_SPEC 0x1B
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#define ARMV7_PERFCTR_TTBR_WRITE 0x1C
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#define ARMV7_PERFCTR_BUS_CYCLES 0x1D
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ARMV7_PERFCTR_CPU_CYCLES = 0xFF
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};
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#define ARMV7_PERFCTR_CPU_CYCLES 0xFF
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/* ARMv7 Cortex-A8 specific event types */
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enum armv7_a8_perf_types {
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ARMV7_A8_PERFCTR_L2_CACHE_ACCESS = 0x43,
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ARMV7_A8_PERFCTR_L2_CACHE_REFILL = 0x44,
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ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS = 0x50,
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ARMV7_A8_PERFCTR_STALL_ISIDE = 0x56,
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};
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#define ARMV7_A8_PERFCTR_L2_CACHE_ACCESS 0x43
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#define ARMV7_A8_PERFCTR_L2_CACHE_REFILL 0x44
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#define ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS 0x50
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#define ARMV7_A8_PERFCTR_STALL_ISIDE 0x56
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/* ARMv7 Cortex-A9 specific event types */
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enum armv7_a9_perf_types {
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ARMV7_A9_PERFCTR_INSTR_CORE_RENAME = 0x68,
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ARMV7_A9_PERFCTR_STALL_ICACHE = 0x60,
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ARMV7_A9_PERFCTR_STALL_DISPATCH = 0x66,
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};
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#define ARMV7_A9_PERFCTR_INSTR_CORE_RENAME 0x68
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#define ARMV7_A9_PERFCTR_STALL_ICACHE 0x60
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#define ARMV7_A9_PERFCTR_STALL_DISPATCH 0x66
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/* ARMv7 Cortex-A5 specific event types */
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enum armv7_a5_perf_types {
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ARMV7_A5_PERFCTR_PREFETCH_LINEFILL = 0xc2,
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ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP = 0xc3,
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};
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#define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL 0xc2
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#define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP 0xc3
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/* ARMv7 Cortex-A15 specific event types */
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enum armv7_a15_perf_types {
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ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ = 0x40,
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ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE = 0x41,
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ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ = 0x42,
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ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE = 0x43,
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#define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ 0x40
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#define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41
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#define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ 0x42
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#define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE 0x43
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ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ = 0x4C,
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ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE = 0x4D,
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#define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ 0x4C
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#define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE 0x4D
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ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ = 0x50,
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ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE = 0x51,
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ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ = 0x52,
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ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE = 0x53,
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#define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ 0x50
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#define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51
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#define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ 0x52
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#define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE 0x53
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ARMV7_A15_PERFCTR_PC_WRITE_SPEC = 0x76,
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};
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#define ARMV7_A15_PERFCTR_PC_WRITE_SPEC 0x76
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/* ARMv7 Cortex-A12 specific event types */
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enum armv7_a12_perf_types {
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ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ = 0x40,
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ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE = 0x41,
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#define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ 0x40
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#define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41
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ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ = 0x50,
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ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE = 0x51,
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#define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ 0x50
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#define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51
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ARMV7_A12_PERFCTR_PC_WRITE_SPEC = 0x76,
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#define ARMV7_A12_PERFCTR_PC_WRITE_SPEC 0x76
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ARMV7_A12_PERFCTR_PF_TLB_REFILL = 0xe7,
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};
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#define ARMV7_A12_PERFCTR_PF_TLB_REFILL 0xe7
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/* ARMv7 Krait specific event types */
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enum krait_perf_types {
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KRAIT_PMRESR0_GROUP0 = 0xcc,
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KRAIT_PMRESR1_GROUP0 = 0xd0,
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KRAIT_PMRESR2_GROUP0 = 0xd4,
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KRAIT_VPMRESR0_GROUP0 = 0xd8,
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#define KRAIT_PMRESR0_GROUP0 0xcc
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#define KRAIT_PMRESR1_GROUP0 0xd0
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#define KRAIT_PMRESR2_GROUP0 0xd4
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#define KRAIT_VPMRESR0_GROUP0 0xd8
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KRAIT_PERFCTR_L1_ICACHE_ACCESS = 0x10011,
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KRAIT_PERFCTR_L1_ICACHE_MISS = 0x10010,
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#define KRAIT_PERFCTR_L1_ICACHE_ACCESS 0x10011
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#define KRAIT_PERFCTR_L1_ICACHE_MISS 0x10010
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KRAIT_PERFCTR_L1_ITLB_ACCESS = 0x12222,
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KRAIT_PERFCTR_L1_DTLB_ACCESS = 0x12210,
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};
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#define KRAIT_PERFCTR_L1_ITLB_ACCESS 0x12222
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#define KRAIT_PERFCTR_L1_DTLB_ACCESS 0x12210
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/* ARMv7 Scorpion specific event types */
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enum scorpion_perf_types {
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SCORPION_LPM0_GROUP0 = 0x4c,
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SCORPION_LPM1_GROUP0 = 0x50,
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SCORPION_LPM2_GROUP0 = 0x54,
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SCORPION_L2LPM_GROUP0 = 0x58,
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SCORPION_VLPM_GROUP0 = 0x5c,
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#define SCORPION_LPM0_GROUP0 0x4c
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#define SCORPION_LPM1_GROUP0 0x50
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#define SCORPION_LPM2_GROUP0 0x54
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#define SCORPION_L2LPM_GROUP0 0x58
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#define SCORPION_VLPM_GROUP0 0x5c
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SCORPION_ICACHE_ACCESS = 0x10053,
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SCORPION_ICACHE_MISS = 0x10052,
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#define SCORPION_ICACHE_ACCESS 0x10053
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#define SCORPION_ICACHE_MISS 0x10052
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SCORPION_DTLB_ACCESS = 0x12013,
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SCORPION_DTLB_MISS = 0x12012,
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#define SCORPION_DTLB_ACCESS 0x12013
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#define SCORPION_DTLB_MISS 0x12012
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SCORPION_ITLB_MISS = 0x12021,
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};
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#define SCORPION_ITLB_MISS 0x12021
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/*
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* Cortex-A8 HW events mapping
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