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csky: Fixup msa highest 3 bits mask

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[ Upstream commit 165f2d2858013253042809df082b8df7e34e86d7 ]

Just as comment mentioned, the msa format:

 cr<30/31, 15> MSA register format:
 31 - 29 | 28 - 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
   BA     Reserved  SH  WA  B   SO SEC  C   D   V

So we should shift 29 bits not 28 bits for mask

Signed-off-by: Liu Yibin <jiulong@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Liu Yibin 2020-04-21 15:56:28 +08:00 committed by Greg Kroah-Hartman
parent e104bd8554
commit f3f23f4c64
2 changed files with 4 additions and 4 deletions
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4
arch/csky/abiv1/inc/abi/entry.h
View File

@ -167,8 +167,8 @@
* BA Reserved C D V * BA Reserved C D V
*/ */
cprcr r6, cpcr30 cprcr r6, cpcr30
lsri r6, 28 lsri r6, 29
lsli r6, 28 lsli r6, 29
addi r6, 0xe addi r6, 0xe
cpwcr r6, cpcr30 cpwcr r6, cpcr30

4
arch/csky/abiv2/inc/abi/entry.h
View File

@ -225,8 +225,8 @@
*/ */
mfcr r6, cr<30, 15> /* Get MSA0 */ mfcr r6, cr<30, 15> /* Get MSA0 */
2: 2:
lsri r6, 28 lsri r6, 29
lsli r6, 28 lsli r6, 29
addi r6, 0x1ce addi r6, 0x1ce
mtcr r6, cr<30, 15> /* Set MSA0 */ mtcr r6, cr<30, 15> /* Set MSA0 */