net: mscc: ocelot: do not force Felix MACs at lower speeds than gigabit
In the LS1028A, the VSC9959 switch was integrated with an NXP PCS which performs SGMII AN and rate adaptation autonomously. The MAC does not need to know about this, and forcing the MAC speed to something else, when connected to a 10/100 link partner, actually breaks the GMII internal link between the MAC and the PCS. Add a quirk system in the ocelot driver, and a first quirk called "PCS performs rate adaptation", to distinguish the VSC7514 from the VSC9959 regarding this behavior. Signed-off-by: Catalin Horghidan <catalin.horghidan@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
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@ -249,6 +249,7 @@ static int felix_init_structs(struct felix *felix, int num_phys_ports)
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ocelot->num_stats = felix->info->num_stats;
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ocelot->shared_queue_sz = felix->info->shared_queue_sz;
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ocelot->ops = felix->info->ops;
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ocelot->quirks = felix->info->quirks;
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base = pci_resource_start(felix->pdev, felix->info->pci_bar);
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@ -18,6 +18,7 @@ struct felix_info {
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unsigned int num_stats;
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int num_ports;
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int pci_bar;
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unsigned long quirks;
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};
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extern struct felix_info felix_info_vsc9959;
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@ -584,4 +584,5 @@ struct felix_info felix_info_vsc9959 = {
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.shared_queue_sz = 128 * 1024,
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.num_ports = 6,
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.pci_bar = 4,
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.quirks = OCELOT_PCS_PERFORMS_RATE_ADAPTATION,
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};
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@ -409,27 +409,32 @@ static u16 ocelot_wm_enc(u16 value)
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void ocelot_adjust_link(struct ocelot *ocelot, int port,
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struct phy_device *phydev)
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{
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int speed, mac_speed, mac_mode = DEV_MAC_MODE_CFG_FDX_ENA;
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struct ocelot_port *ocelot_port = ocelot->ports[port];
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int speed, mode = 0;
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switch (phydev->speed) {
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if (ocelot->quirks & OCELOT_PCS_PERFORMS_RATE_ADAPTATION)
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speed = SPEED_1000;
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else
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speed = phydev->speed;
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switch (speed) {
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case SPEED_10:
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speed = OCELOT_SPEED_10;
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mac_speed = OCELOT_SPEED_10;
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break;
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case SPEED_100:
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speed = OCELOT_SPEED_100;
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mac_speed = OCELOT_SPEED_100;
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break;
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case SPEED_1000:
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speed = OCELOT_SPEED_1000;
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mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
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mac_speed = OCELOT_SPEED_1000;
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mac_mode |= DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
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break;
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case SPEED_2500:
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speed = OCELOT_SPEED_2500;
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mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
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mac_speed = OCELOT_SPEED_2500;
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mac_mode |= DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
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break;
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default:
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dev_err(ocelot->dev, "Unsupported PHY speed on port %d: %d\n",
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port, phydev->speed);
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port, speed);
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return;
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}
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@ -439,8 +444,7 @@ void ocelot_adjust_link(struct ocelot *ocelot, int port,
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return;
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/* Only full duplex supported for now */
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ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA |
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mode, DEV_MAC_MODE_CFG);
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ocelot_port_writel(ocelot_port, mac_mode, DEV_MAC_MODE_CFG);
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if (ocelot->ops->pcs_init)
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ocelot->ops->pcs_init(ocelot, port);
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@ -451,11 +455,11 @@ void ocelot_adjust_link(struct ocelot *ocelot, int port,
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/* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of
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* reset */
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ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed),
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ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed),
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DEV_CLOCK_CFG);
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/* No PFC */
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ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed),
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ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(mac_speed),
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ANA_PFC_PFC_CFG, port);
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/* Core: Enable port for frame transfer */
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@ -469,7 +473,7 @@ void ocelot_adjust_link(struct ocelot *ocelot, int port,
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SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA |
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SYS_MAC_FC_CFG_ZERO_PAUSE_ENA |
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SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
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SYS_MAC_FC_CFG_FC_LINK_SPEED(speed),
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SYS_MAC_FC_CFG_FC_LINK_SPEED(mac_speed),
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SYS_MAC_FC_CFG, port);
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ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
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}
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@ -404,6 +404,11 @@ enum ocelot_tag_prefix {
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OCELOT_TAG_PREFIX_LONG,
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};
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/* Hardware quirks (differences between switch instantiations) */
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enum {
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OCELOT_PCS_PERFORMS_RATE_ADAPTATION = BIT(0),
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};
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struct ocelot;
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struct ocelot_ops {
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@ -464,6 +469,8 @@ struct ocelot {
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struct delayed_work stats_work;
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struct workqueue_struct *stats_queue;
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unsigned long quirks;
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u8 ptp:1;
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struct ptp_clock *ptp_clock;
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struct ptp_clock_info ptp_info;
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