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[ARM] 5264/2: [AT91] Suspend-to-RAM disables main oscillator
This patch adds support for a low(er)-power suspend-to-RAM. In addition to the SDRAM being put into self-refresh mode, the Master Clock is set to the Slow-clock rate (32Khz) and PLLA & PLLB are disabled. Certain peripherals are therefore also disabled, and thus cannot be used as wakeup sources. This patch has been included in the AT91 patches in various forms since 2.6.19 and a number of people have worked or commented on it, most notably: Savin Zlobec (for the original AT91RM9200 support) Anti Sullin (for the SAM9260 version) David Brownell, etc. Signed-off-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Andrew Victor
Russell King
parent
77789ad8b1
commit
eaad2db03c
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@ -323,6 +323,19 @@ config AT91_PROGRAMMABLE_CLOCKS
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Select this if you need to program one or more of the PCK0..PCK3
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programmable clock outputs.
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config AT91_SLOW_CLOCK
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bool "Suspend-to-RAM disables main oscillator"
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depends on SUSPEND
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help
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Select this if you want Suspend-to-RAM to save the most power
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possible (without powering off the CPU) by disabling the PLLs
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and main oscillator so that only the 32 KiHz clock is available.
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When only that slow-clock is available, some peripherals lose
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functionality. Many can't issue wakeup events unless faster
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clocks are available. Some lose their operating state and
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need to be completely re-initialized.
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config AT91_TIMER_HZ
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int "Kernel HZ (jiffies per second)"
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range 32 1024
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@ -65,6 +65,7 @@ obj-y += leds.o
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# Power Management
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obj-$(CONFIG_PM) += pm.o
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obj-$(CONFIG_AT91_SLOW_CLOCK) += pm_slowclock.o
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ifeq ($(CONFIG_PM_DEBUG),y)
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CFLAGS_pm.o += -DDEBUG
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283
arch/arm/mach-at91/pm_slowclock.S
Normal file
283
arch/arm/mach-at91/pm_slowclock.S
Normal file
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@ -0,0 +1,283 @@
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/*
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* arch/arm/mach-at91/pm_slow_clock.S
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*
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* Copyright (C) 2006 Savin Zlobec
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*
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* AT91SAM9 support:
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* Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/linkage.h>
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#include <mach/hardware.h>
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#include <mach/at91_pmc.h>
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#ifdef CONFIG_ARCH_AT91RM9200
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#include <mach/at91rm9200_mc.h>
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#elif defined(CONFIG_ARCH_AT91CAP9)
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#include <mach/at91cap9_ddrsdr.h>
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#else
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#include <mach/at91sam9_sdramc.h>
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#endif
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#ifdef CONFIG_ARCH_AT91SAM9263
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/*
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* FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
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* handle those cases both here and in the Suspend-To-RAM support.
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*/
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#define AT91_SDRAMC AT91_SDRAMC0
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#warning Assuming EB1 SDRAM controller is *NOT* used
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#endif
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/*
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* When SLOWDOWN_MASTER_CLOCK is defined we will also slow down the Master
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* clock during suspend by adjusting its prescalar and divisor.
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* NOTE: This hasn't been shown to be stable on SAM9s; and on the RM9200 there
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* are errata regarding adjusting the prescalar and divisor.
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*/
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#undef SLOWDOWN_MASTER_CLOCK
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#define MCKRDY_TIMEOUT 1000
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#define MOSCRDY_TIMEOUT 1000
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#define PLLALOCK_TIMEOUT 1000
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#define PLLBLOCK_TIMEOUT 1000
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/*
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* Wait until master clock is ready (after switching master clock source)
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*/
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.macro wait_mckrdy
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mov r4, #MCKRDY_TIMEOUT
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1: sub r4, r4, #1
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cmp r4, #0
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beq 2f
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ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
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tst r3, #AT91_PMC_MCKRDY
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beq 1b
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2:
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.endm
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/*
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* Wait until master oscillator has stabilized.
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*/
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.macro wait_moscrdy
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mov r4, #MOSCRDY_TIMEOUT
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1: sub r4, r4, #1
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cmp r4, #0
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beq 2f
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ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
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tst r3, #AT91_PMC_MOSCS
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beq 1b
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2:
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.endm
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/*
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* Wait until PLLA has locked.
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*/
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.macro wait_pllalock
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mov r4, #PLLALOCK_TIMEOUT
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1: sub r4, r4, #1
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cmp r4, #0
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beq 2f
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ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
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tst r3, #AT91_PMC_LOCKA
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beq 1b
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2:
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.endm
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/*
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* Wait until PLLB has locked.
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*/
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.macro wait_pllblock
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mov r4, #PLLBLOCK_TIMEOUT
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1: sub r4, r4, #1
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cmp r4, #0
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beq 2f
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ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
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tst r3, #AT91_PMC_LOCKB
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beq 1b
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2:
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.endm
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.text
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ENTRY(at91_slow_clock)
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/* Save registers on stack */
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stmfd sp!, {r0 - r12, lr}
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/*
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* Register usage:
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* R1 = Base address of AT91_PMC
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* R2 = Base address of AT91_SDRAMC (or AT91_SYS on AT91RM9200)
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* R3 = temporary register
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* R4 = temporary register
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*/
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ldr r1, .at91_va_base_pmc
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ldr r2, .at91_va_base_sdramc
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/* Drain write buffer */
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mcr p15, 0, r0, c7, c10, 4
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#ifdef CONFIG_ARCH_AT91RM9200
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/* Put SDRAM in self-refresh mode */
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mov r3, #1
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str r3, [r2, #AT91_SDRAMC_SRR]
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#elif defined(CONFIG_ARCH_AT91CAP9)
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/* Enable SDRAM self-refresh mode */
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ldr r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
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str r3, .saved_sam9_lpr
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mov r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
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str r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
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#else
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/* Enable SDRAM self-refresh mode */
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ldr r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
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str r3, .saved_sam9_lpr
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mov r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
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str r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
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#endif
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/* Save Master clock setting */
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ldr r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
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str r3, .saved_mckr
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/*
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* Set the Master clock source to slow clock
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*/
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bic r3, r3, #AT91_PMC_CSS
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str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
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wait_mckrdy
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#ifdef SLOWDOWN_MASTER_CLOCK
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/*
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* Set the Master Clock PRES and MDIV fields.
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*
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* See AT91RM9200 errata #27 and #28 for details.
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*/
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mov r3, #0
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str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
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wait_mckrdy
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#endif
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/* Save PLLA setting and disable it */
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ldr r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
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str r3, .saved_pllar
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mov r3, #AT91_PMC_PLLCOUNT
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orr r3, r3, #(1 << 29) /* bit 29 always set */
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str r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
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wait_pllalock
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/* Save PLLB setting and disable it */
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ldr r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
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str r3, .saved_pllbr
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mov r3, #AT91_PMC_PLLCOUNT
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str r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
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wait_pllblock
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/* Turn off the main oscillator */
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ldr r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
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bic r3, r3, #AT91_PMC_MOSCEN
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str r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
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/* Wait for interrupt */
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mcr p15, 0, r0, c7, c0, 4
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/* Turn on the main oscillator */
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ldr r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
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orr r3, r3, #AT91_PMC_MOSCEN
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str r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
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wait_moscrdy
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/* Restore PLLB setting */
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ldr r3, .saved_pllbr
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str r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
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wait_pllblock
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/* Restore PLLA setting */
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ldr r3, .saved_pllar
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str r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
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wait_pllalock
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#ifdef SLOWDOWN_MASTER_CLOCK
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/*
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* First set PRES if it was not 0,
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* than set CSS and MDIV fields.
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*
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* See AT91RM9200 errata #27 and #28 for details.
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*/
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ldr r3, .saved_mckr
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tst r3, #AT91_PMC_PRES
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beq 2f
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and r3, r3, #AT91_PMC_PRES
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str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
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wait_mckrdy
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#endif
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/*
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* Restore master clock setting
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*/
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2: ldr r3, .saved_mckr
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str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
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wait_mckrdy
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#ifdef CONFIG_ARCH_AT91RM9200
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/* Do nothing - self-refresh is automatically disabled. */
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#elif defined(CONFIG_ARCH_AT91CAP9)
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/* Restore LPR on AT91CAP9 */
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ldr r3, .saved_sam9_lpr
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str r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
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#else
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/* Restore LPR on AT91SAM9 */
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ldr r3, .saved_sam9_lpr
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str r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
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#endif
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/* Restore registers, and return */
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ldmfd sp!, {r0 - r12, pc}
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.saved_mckr:
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.word 0
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.saved_pllar:
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.word 0
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.saved_pllbr:
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.word 0
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.saved_sam9_lpr:
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.word 0
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.at91_va_base_pmc:
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.word AT91_VA_BASE_SYS + AT91_PMC
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#ifdef CONFIG_ARCH_AT91RM9200
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.at91_va_base_sdramc:
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.word AT91_VA_BASE_SYS
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#elif defined(CONFIG_ARCH_AT91CAP9)
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.at91_va_base_sdramc:
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.word AT91_VA_BASE_SYS + AT91_DDRSDRC
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#else
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.at91_va_base_sdramc:
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.word AT91_VA_BASE_SYS + AT91_SDRAMC
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#endif
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ENTRY(at91_slow_clock_sz)
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.word .-at91_slow_clock
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