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Amlogic 64-bit DT changes for v4.19, round 2 

- new SoC: S905W
 - new boards: based on S905W: Amlogic P281, Oranth Tanix TX3 Mini
 - AXG: add DT for new audio clock controller
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Merge tag 'amlogic-dt64-2-1' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt

Amlogic 64-bit DT changes for v4.19, round 2
- new SoC: S905W
- new boards: based on S905W: Amlogic P281, Oranth Tanix TX3 Mini
- AXG: add DT for new audio clock controller

* tag 'amlogic-dt64-2-1' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  ARM64: dts: meson-gxl: add support for the Oranth Tanix TX3 Mini
  ARM64: dts: meson-gxl: add support for the S905W SoC and the P281 board
  dt-bindings: arm: amlogic: Add support for the Oranth Tanix TX3 Mini
  dt-bindings: arm: amlogic: Add support for GXL S905W and the P281 board
  dt-bindings: add vendor prefix for Shenzhen Oranth Technology Co., Ltd.
  ARM64: dts: meson-axg: add the audio clock controller
  clk: meson: expose GEN_CLK clkid
  clk: meson-axg: add pcie and mipi clock bindings
  dt-bindings: clock: add meson axg audio clock controller bindings

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2018-07-25 23:53:39 -07:00
parent 295d44ae78 aaa080fa7e
commit ea537363c7
10 changed files with 245 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
Documentation/devicetree/bindings/arm/amlogic.txt
View File

@ -45,6 +45,10 @@ Boards with the Amlogic Meson GXL S805X SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s805x", "amlogic,meson-gxl";
Boards with the Amlogic Meson GXL S905W SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s905w", "amlogic,meson-gxl";
Boards with the Amlogic Meson GXM S912 SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s912", "amlogic,meson-gxm";
@ -85,6 +89,9 @@ Board compatible values (alphabetically, grouped by SoC):
- "amlogic,p241" (Meson gxl s805x)
- "amlogic,p281" (Meson gxl s905w)
- "oranth,tx3-mini" (Meson gxl s905w)
- "amlogic,q200" (Meson gxm s912)
- "amlogic,q201" (Meson gxm s912)
- "khadas,vim2" (Meson gxm s912)

56
Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt Normal file
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@ -0,0 +1,56 @@
* Amlogic AXG Audio Clock Controllers
The Amlogic AXG audio clock controller generates and supplies clock to the
other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
devices.
Required Properties:
- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D
- reg : physical base address of the clock controller and length of
memory mapped region.
- clocks : a list of phandle + clock-specifier pairs for the clocks listed
in clock-names.
- clock-names : must contain the following:
* "pclk" - Main peripheral bus clock
may contain the following:
* "mst_in[0-7]" - 8 input plls to generate clock signals
* "slv_sclk[0-9]" - 10 slave bit clocks provided by external
components.
* "slv_lrclk[0-9]" - 10 slave sample clocks provided by external
components.
- resets : phandle of the internal reset line
- #clock-cells : should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be
used in device tree sources.
Example:
clkc_audio: clock-controller@0 {
compatible = "amlogic,axg-audio-clkc";
reg = <0x0 0x0 0x0 0xb4>;
#clock-cells = <1>;
clocks = <&clkc CLKID_AUDIO>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL3>,
<&clkc CLKID_HIFI_PLL>,
<&clkc CLKID_FCLK_DIV3>,
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_GP0_PLL>;
clock-names = "pclk",
"mst_in0",
"mst_in1",
"mst_in2",
"mst_in3",
"mst_in4",
"mst_in5",
"mst_in6",
"mst_in7";
resets = <&reset RESET_AUDIO>;
};

1
Documentation/devicetree/bindings/vendor-prefixes.txt
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@ -273,6 +273,7 @@ opalkelly Opal Kelly Incorporated
opencores OpenCores.org
openrisc OpenRISC.io
option Option NV
oranth Shenzhen Oranth Technology Co., Ltd.
ORCL Oracle Corporation
orisetech Orise Technology
ortustech Ortus Technology Co., Ltd.

2
arch/arm64/boot/dts/amlogic/Makefile
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@ -18,6 +18,8 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-p281.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-tx3-mini.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb

36
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
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@ -6,6 +6,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/axg-audio-clkc.h>
#include <dt-bindings/clock/axg-clkc.h>
#include <dt-bindings/clock/axg-aoclkc.h>
#include <dt-bindings/gpio/meson-axg-gpio.h>
@ -155,6 +156,41 @@
};
};
audio: bus@ff642000 {
compatible = "simple-bus";
reg = <0x0 0xff642000 0x0 0x2000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
clkc_audio: clock-controller@0 {
compatible = "amlogic,axg-audio-clkc";
reg = <0x0 0x0 0x0 0xb4>;
#clock-cells = <1>;
clocks = <&clkc CLKID_AUDIO>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL3>,
<&clkc CLKID_HIFI_PLL>,
<&clkc CLKID_FCLK_DIV3>,
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_GP0_PLL>;
clock-names = "pclk",
"mst_in0",
"mst_in1",
"mst_in2",
"mst_in3",
"mst_in4",
"mst_in5",
"mst_in6",
"mst_in7";
resets = <&reset RESET_AUDIO>;
};
};
cbus: bus@ffd00000 {
compatible = "simple-bus";
reg = <0x0 0xffd00000 0x0 0x25000>;

22
arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts Normal file
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@ -0,0 +1,22 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
* Based on meson-gxl-s905d-p231.dts:
* - Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
*/
/dts-v1/;
#include "meson-gxl-s905x.dtsi"
#include "meson-gx-p23x-q20x.dtsi"
/ {
compatible = "amlogic,p281", "amlogic,s905w", "amlogic,meson-gxl";
model = "Amlogic Meson GXL (S905W) P281 Development Board";
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
};

22
arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts Normal file
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@ -0,0 +1,22 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
* Based on meson-gxl-s905d-p231.dts:
* - Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
*/
/dts-v1/;
#include "meson-gxl-s905x.dtsi"
#include "meson-gx-p23x-q20x.dtsi"
/ {
compatible = "oranth,tx3-mini", "amlogic,s905w", "amlogic,meson-gxl";
model = "Oranth Tanix TX3 Mini";
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>; /* 1 GiB or 2 GiB */
};
};

94
include/dt-bindings/clock/axg-audio-clkc.h Normal file
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@ -0,0 +1,94 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Copyright (c) 2018 Baylibre SAS.
* Author: Jerome Brunet <jbrunet@baylibre.com>
*/
#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
#define __AXG_AUDIO_CLKC_BINDINGS_H
#define AUD_CLKID_SLV_SCLK0 9
#define AUD_CLKID_SLV_SCLK1 10
#define AUD_CLKID_SLV_SCLK2 11
#define AUD_CLKID_SLV_SCLK3 12
#define AUD_CLKID_SLV_SCLK4 13
#define AUD_CLKID_SLV_SCLK5 14
#define AUD_CLKID_SLV_SCLK6 15
#define AUD_CLKID_SLV_SCLK7 16
#define AUD_CLKID_SLV_SCLK8 17
#define AUD_CLKID_SLV_SCLK9 18
#define AUD_CLKID_SLV_LRCLK0 19
#define AUD_CLKID_SLV_LRCLK1 20
#define AUD_CLKID_SLV_LRCLK2 21
#define AUD_CLKID_SLV_LRCLK3 22
#define AUD_CLKID_SLV_LRCLK4 23
#define AUD_CLKID_SLV_LRCLK5 24
#define AUD_CLKID_SLV_LRCLK6 25
#define AUD_CLKID_SLV_LRCLK7 26
#define AUD_CLKID_SLV_LRCLK8 27
#define AUD_CLKID_SLV_LRCLK9 28
#define AUD_CLKID_DDR_ARB 29
#define AUD_CLKID_PDM 30
#define AUD_CLKID_TDMIN_A 31
#define AUD_CLKID_TDMIN_B 32
#define AUD_CLKID_TDMIN_C 33
#define AUD_CLKID_TDMIN_LB 34
#define AUD_CLKID_TDMOUT_A 35
#define AUD_CLKID_TDMOUT_B 36
#define AUD_CLKID_TDMOUT_C 37
#define AUD_CLKID_FRDDR_A 38
#define AUD_CLKID_FRDDR_B 39
#define AUD_CLKID_FRDDR_C 40
#define AUD_CLKID_TODDR_A 41
#define AUD_CLKID_TODDR_B 42
#define AUD_CLKID_TODDR_C 43
#define AUD_CLKID_LOOPBACK 44
#define AUD_CLKID_SPDIFIN 45
#define AUD_CLKID_SPDIFOUT 46
#define AUD_CLKID_RESAMPLE 47
#define AUD_CLKID_POWER_DETECT 48
#define AUD_CLKID_MST_A_MCLK 49
#define AUD_CLKID_MST_B_MCLK 50
#define AUD_CLKID_MST_C_MCLK 51
#define AUD_CLKID_MST_D_MCLK 52
#define AUD_CLKID_MST_E_MCLK 53
#define AUD_CLKID_MST_F_MCLK 54
#define AUD_CLKID_SPDIFOUT_CLK 55
#define AUD_CLKID_SPDIFIN_CLK 56
#define AUD_CLKID_PDM_DCLK 57
#define AUD_CLKID_PDM_SYSCLK 58
#define AUD_CLKID_MST_A_SCLK 79
#define AUD_CLKID_MST_B_SCLK 80
#define AUD_CLKID_MST_C_SCLK 81
#define AUD_CLKID_MST_D_SCLK 82
#define AUD_CLKID_MST_E_SCLK 83
#define AUD_CLKID_MST_F_SCLK 84
#define AUD_CLKID_MST_A_LRCLK 86
#define AUD_CLKID_MST_B_LRCLK 87
#define AUD_CLKID_MST_C_LRCLK 88
#define AUD_CLKID_MST_D_LRCLK 89
#define AUD_CLKID_MST_E_LRCLK 90
#define AUD_CLKID_MST_F_LRCLK 91
#define AUD_CLKID_TDMIN_A_SCLK_SEL 116
#define AUD_CLKID_TDMIN_B_SCLK_SEL 117
#define AUD_CLKID_TDMIN_C_SCLK_SEL 118
#define AUD_CLKID_TDMIN_LB_SCLK_SEL 119
#define AUD_CLKID_TDMOUT_A_SCLK_SEL 120
#define AUD_CLKID_TDMOUT_B_SCLK_SEL 121
#define AUD_CLKID_TDMOUT_C_SCLK_SEL 122
#define AUD_CLKID_TDMIN_A_SCLK 123
#define AUD_CLKID_TDMIN_B_SCLK 124
#define AUD_CLKID_TDMIN_C_SCLK 125
#define AUD_CLKID_TDMIN_LB_SCLK 126
#define AUD_CLKID_TDMOUT_A_SCLK 127
#define AUD_CLKID_TDMOUT_B_SCLK 128
#define AUD_CLKID_TDMOUT_C_SCLK 129
#define AUD_CLKID_TDMIN_A_LRCLK 130
#define AUD_CLKID_TDMIN_B_LRCLK 131
#define AUD_CLKID_TDMIN_C_LRCLK 132
#define AUD_CLKID_TDMIN_LB_LRCLK 133
#define AUD_CLKID_TDMOUT_A_LRCLK 134
#define AUD_CLKID_TDMOUT_B_LRCLK 135
#define AUD_CLKID_TDMOUT_C_LRCLK 136
#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */

4
include/dt-bindings/clock/axg-clkc.h
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@ -68,5 +68,9 @@
#define CLKID_SD_EMMC_B_CLK0 59
#define CLKID_SD_EMMC_C_CLK0 60
#define CLKID_HIFI_PLL 69
#define CLKID_PCIE_CML_EN0 79
#define CLKID_PCIE_CML_EN1 80
#define CLKID_MIPI_ENABLE 81
#define CLKID_GEN_CLK 84
#endif /* __AXG_CLKC_H */

1
include/dt-bindings/clock/gxbb-clkc.h
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@ -127,5 +127,6 @@
#define CLKID_VAPB 140
#define CLKID_VDEC_1 153
#define CLKID_VDEC_HEVC 156
#define CLKID_GEN_CLK 159
#endif /* __GXBB_CLKC_H */